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  • RTL Foundations36
  • Combinational Design25
  • Sequential Design27
  • FSM & Control27
  • Timing & Clocking39
  • Reset & CDC34
  • Memory & Buses57
  • Advanced RTL28
  • Senior & Interview76
    • Low-Power RTL Hub
    • DFT and Scan Hub
    • Physical Awareness Hub
    • Waveform Debug Hub
      • Debug hierarchy before touching code
      • Controlled dumps and trigger capture
      • Waveform bug patterns: latch and race
      • Handshake protocol violation
    • STA and ECO Hub
    • RTL-to-Implementation Closure
    • DFT-Ready RTL
    • Capstone: Resilient Streaming Peripheral
    • Principal Design Review
    • Senior RTL Interview Questions & Model Answers
  • Glossary and Notation
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‹Waveform Debug Hub
  1. Topics
  2. RTL Design
  3. Senior & Interview
  4. Waveform Debug Hub
  5. Controlled dumps and trigger capture

Part 9 · Senior · Senior

Controlled dumps and trigger capture

Gate waveform dumps behind plusargs and arm triggers on violations instead of dumping everything.

On this page

    Why this matters

    A full-design dump on a long run slows every simulation and buries the event. A bare $stop in a monitor halts every regression run.

    After this lesson you can: gate dumps behind a plusarg, arm a trigger on a violation, and explain why a window needs a replay.

    Dump only what is needed

    Wave files grow with scope and time. Dumping a full design for a long run slows simulation and buries the event.

    Dump the suspect hierarchy, and only for runs that need waves. Heavy dumping stays behind a plusarg or a compile define.

    Gate dumps behind plusargs

    The gate below dumps nothing by default. Adding +WAVE_ON to the command line enables the dump without recompiling.

    design.sv
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    // snippet
    `timescale 1ns/1ps
    initial begin
      if ($test$plusargs("WAVE_ON")) begin
        $dumpfile("trig_cnt.vcd");
        $dumpvars(0, tb_trig_cnt);
      end
    end

    Arm triggers on violations

    Rare errors drown in long logs. A trigger watches a protocol condition and prints a snapshot when it fires.

    The testbench below arms a trigger on count 10 and prints one line. The trigger reads the DUT's count port; a hierarchical reference such as dut.count would also work, but only in testbench code, never in synthesizable RTL.

    Common pitfall

    A bare $stop in a monitor halts every regression run. Print the snapshot and finish conditionally instead, so the trigger helps in interactive runs without blocking batch runs.

    Interview

    “A test fails once in 10,000 runs. How is it captured?” Arm a trigger on the failure signature, rerun the seed with +WAVE_ON, and take the snapshot around the firing.

    Check yourself A regression suite runs thousands of seeds. Should dumps stay on?

    No. Dumps stay off by default and turn on with +WAVE_ON for the failing seed only. Always-on dumps slow every run and fill disks.

    Check yourself A trigger fires on every clock instead of once. What is the usual cause?

    The condition is too broad, often a level instead of an exact value. The testbench counts firings so a noisy trigger fails loudly.

    Testbench

    A counter with a trigger at count 10. With +WAVE_ON, dump activity is enabled only from count 8 through count 12, preserving two cycles of context on each side. This is a deterministic replay window: first reproduce/log the failure cycle, then rerun with a window starting before it. An unpredictable first-run trigger needs simulator circular/pre-trigger capture or retained transaction history; $dumpon cannot recover events from the past.

    With +WAVE_ON the dump stays off except from count 8 to count 12, which brackets the trigger at count 10 by two counts on each side.

    Read the timeline left to right along the count axis. The shaded band is the only stretch written to the wave file.

    • Counts 0 to 7: $dumpoff keeps the file to its header.

    • Counts 8 to 12: $dumpon records two counts of context before and after the event.

    • Count 10: the trigger prints one snapshot; the bench fails if it fires more than once.

    trig_cnt.sv
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    `timescale 1ns/1ps
    module trig_cnt (
      input  logic       clk, rst_n,
      output logic [7:0] count
    );
      always_ff @(posedge clk) begin
        if (!rst_n) count <= 8'd0;
        else        count <= count + 8'd1;
      end
    endmodule
    

    Remember

    • Dumps are off by default; +WAVE_ON turns them on for the failing seed without recompiling.

    • A trigger prints a snapshot and finishes conditionally, never a bare $stop.

    • $dumpon cannot recover the past: reproduce the failure cycle, then rerun with a window that starts before it.

    Keep going

    • Interview: run a mock interview on this topic

    Related topics

    • Waveform bug patterns: latch and race

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    See also

    • Handshake protocol violation