RTL defines storage and combinational semantics; supported templates make that intent recognizable to synthesis. Template compatibility does not guarantee a particular cell. Final resources depend on tool, target, size, ports, constraints and optimization; inspect mapping reports.
Intended hardware | Canonical shape | Lesson |
|---|---|---|
Flip-flop with enable |
| |
Synchronous RAM | Array, clocked write, registered read | |
Combinational logic | Full assignment on every path |
4 lessons, about 23 min
Compare the array's depth, width, read latency, reset and port/collision requirements with the selected target's supported memory templates. Array reset or unsupported ports may prevent memory mapping. Asynchronous reads can use LUT RAM on supported FPGAs, though they are incompatible with many synchronous block RAMs. Read the inference diagnostics and mapped resource counts before changing RTL.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Inference-focused coding style
Reset priority, the hold path and the arithmetic width set the hardware; the number of processes does not.
Both counters map to the same 23 iCE40 cells: 8 enable flops, 9 LUTs and 6 carry cells.
Compare reports under the same tool version, target and options before drawing a PPA conclusion.
Rule of thumb: write the template the tool recognises, then check the report.
Inferring flip-flops and RAM
A clocked process infers storage; reset comes first, then the enable guard.
Many block RAMs need synchronous reads, no array reset and supported port counts.
State the collision policy: a same-cycle write and read returns the old word, and the new word shows in a later read.
Rule of thumb: choose the latency and resource first, then write the template that maps to it.
Latch avoidance and case semantics
Assign a default before the branch, or add the missing branch; otherwise a latch is inferred.
Plain case with a default is the safe choice, and an X or Z select lands in the default.
Unique and priority add match-count diagnostics and synthesis assumptions; a default removes the no-match check, not unique's overlap check.
Rule of thumb: every output gets a value on every path before the case starts.
Reading a synthesis report
Latch and driver warnings come early, in proc and check. The final check can report 0 problems after the optimiser has hidden them.
A removed or constant flop gives no warning: look for D = Q and constant-bit messages, and compare the flop count with your own.
Run check -assert straight after proc so driver problems fail the run instead of scrolling past.
Rule of thumb: count the flops in the RTL before you open stat; a different number is a bug until it is explained.
Mini project: a reusable FIFO IP with package, interface, assertions and a formal check
Practice question: Parameterised single-port synchronous RAM
Code lab: SRAM model 16x8
Practice question: Incomplete case and unique0: simulation versus synthesis
Practice question: Level-sensitive latch: when it is risky
Interview: run a mock interview on this topic
The example benches are finite digital checks. Executed with Icarus Verilog 13.0 (2026-10-16): each prints PASS. The synthesis-report lesson shows real Yosys output on generic cells; no formal, sign-off timing or physical measurements are reported here.