Binary and Hexadecimal Conversion

Hex ↔ binary

One hex digit = 4 bits. Memorize powers of two through 2^16 for mask work.

Conversion chart (nibble map)

HEX  BIN     HEX  BIN
 0    0000     8    1000
 1    0001     9    1001
 2    0010     A    1010
 3    0011     B    1011
 4    0100     C    1100
 5    0101     D    1101
 6    0110     E    1110
 7    0111     F    1111

Mask patterns in RTL

// Byte extract from 32-bit word
wire [7:0] byte1 = word[15:8];
wire [7:0] byte0 = word[7:0];

// Set bit 5, clear bit 3
word <= (word | (1 << 5)) & ~(1 << 3);

Key takeaways

• Register dumps in hex — learn to spot sign bits and field boundaries.

• Use underscores in literals: 8'hFF, 32'hDEAD_BEEF for readability.

Common pitfalls

• Wrong nibble alignment when parsing bus transactions.

• Forgetting 0x prefix vs Verilog 'h radix in different tools.

Deep dive

This lesson deepens Binary and Hexadecimal Conversion within foundations. Senior reviewers expect you to connect mechanism to HDL fluency, width, and simulation habits — not just define terms.

Start from the spec invariant: what must always be true each cycle? Write it as a Boolean relation, timing budget, or protocol rule before coding. That invariant becomes your reference model, assertion, or waveform check.

At tape-out quality, every block needs a sign-off story: lint clean, self-checking TB, width documented. Treat this lesson as building one paragraph of that story for your project documentation.

Architecture and signal flow

BINARY AND HEXADECIMAL CONVERSION

  inputs ──► [foundations] ──► mechanism ──► outputs
                │                │
           number-systems     verify in sim + lint

Worked example (Verilog/SystemVerilog)

Synthesizable pattern for this topic — simulate locally and compare against your reference.

logic signed [7:0] a, b;
logic signed [8:0] sum_wide;
assign sum_wide = a + b;
wire ovf = (a[7]==b[7]) && (sum_wide[7]!=a[7]);

Step-by-step design procedure

1. Write the spec invariant (truth table, timing, or protocol rule).

2. Sketch block diagram — inputs, outputs, clock/reset domains.

3. Code the minimal correct version (no optimizations yet).

4. Run self-checking TB with corners: min, max, reset, idle.

5. Lint and review: width, latch, clock, CDC if applicable.

6. Iterate for timing/area only after functionally proven.

Timing and resource trade-offs

METRIC          TYPICAL LEVER
Logic levels      algebra / pipelining
Register count    retiming / sharing
Wire fanout       duplication / pipeline
Power             clock gating / operand isolation
Debug visibility  status flags / SVA / waveform probes

Debug checklist

• Compare DUT vs reference on every stimulus vector

• Capture first cycle of mismatch — not last

• Log seed and plusargs for random regressions

• Check reset release and clock alignment in TB

• If waveform is ambiguous, add temporary assertions

Interview angle

Explain blocking vs non-blocking with a flop example.

MODEL ANSWER SKELETON
1. MECHANISM — one-sentence technical truth
2. MOTIVATION — why this structure vs alternatives
3. WHEN TO USE / SKIP — scope and assumptions
4. PITFALL — common junior mistake
5. EXAMPLE — Verilog or waveform scenario

Practice exercise

Extend the worked example for "Binary and Hexadecimal Conversion": add one corner case, write a self-checking test, and document one intentional pitfall you avoided. Timebox: 30–45 minutes.

Extended design scenario

Scenario for Binary and Hexadecimal Conversion : You inherit a module with mixed blocking/non-blocking assigns. List every signal, classify comb vs seq, rewrite with always_comb/ff.

Scenario resolution outline

1. Reproduce with minimal TB — one stimulus, one check.

2. Isolate failing cone (logic, FSM state, or bus beat).

3. Fix root cause — not symptom — in RTL or TB alignment.

4. Add regression test that fails without the fix.

5. Document invariant in comment or SVA for permanence.

Additional simulation pattern

// Corner-case TB fragment
initial begin
  for (int i = 0; i < 256; i++) begin
    drive(i[7:0]);
    @(posedge clk);
    check(ref(i[7:0]), dut_out);
  end
end

Synthesis and sign-off notes

• Elaborate clean — no OOM from unconstrained generate

• Constraints cover all clocks and I/O delays

• Cross-check RTL parameters vs integration top

• Attach sim log + seed to code review

Lab exercise (45–60 min)

Implement or extend the worked example for "Binary and Hexadecimal Conversion". Add two new test vectors that target different branches. Write a one-paragraph sign-off note covering function, corners, and what you would still verify in SoC context.

Further reading in this course

Next topics in Part: follow nav_order in sidebar.
Cross-part: timing ↔ sequential, CDC ↔ senior interview,
combinational ↔ foundations number systems.

Extended theory

Foundations are the compression algorithm for the rest of the course: every multi-bit bus, FSM output, and STA report ultimately rests on whether you sized, signed, and simulated the bit-level behavior correctly.

For "Binary and Hexadecimal Conversion", the invariant you defend in review is: behavior matches spec under all legal input sequences, reset flows, and backpressure patterns—not just the happy path shown in introductory diagrams.

Write the invariant as a comment above the module or as an SVA property when possible. Future you (and formal tools) will treat it as the contract.

Waveform reading guide

WAVEFORM NARRATIVE — Binary and Hexadecimal Conversion

cycle 0: reset asserted, outputs safe/idle
cycle 1-2: reset held, clocks running
cycle 3: reset released, first legal inputs
cycle 4+: check output latency (N cycles)
mark FIRST mismatch cycle — not last

Second worked example

Alternate pattern emphasizing debug, coverage, or integration:

// Self-checking scoreboard pattern
class Scoreboard;
  int err;
  function void check(string name, logic [31:0] exp, act);
    if (exp !== act) begin
      $error("%s exp=%h act=%h", name, exp, act);
      err++;
    end
  endfunction
endclass

Comparison: naive vs production

NAIVE APPROACH              PRODUCTION APPROACH
quick hack, one sim vector    self-checking TB + corners
ignore lint warnings          zero new waivers
implicit widths               explicit casts/parameters
undocumented latency          latency in module header comment

Additional interview questions

• Explain Binary and Hexadecimal Conversion to a verification engineer — what would they assert?

• What breaks first at high frequency or low voltage?

• What is your rollback plan if synthesis QoR is unacceptable?

• How would you debug this block with only a 32-bit GPIO trace?

Follow-up interview model answer

Q: What is the #1 mistake with Binary and Hexadecimal Conversion?
A:
  MECHANISM: [core rule in one line]
  MOTIVATION: why teams care in tape-out
  PITFALL: what juniors do wrong
  EXAMPLE: one Verilog line or one waveform event

Hands-on lab part 2

1. Fork the worked example; add one assertion or SVA cover.

2. Inject a bug deliberately; confirm TB or assertion catches it.

3. Write 5-bullet PR description for your change.

4. Peer review: can a teammate enable the block without asking you?

Sign-off evidence checklist

• Directed sim log attached (PASS, seed noted)

• Lint report clean for touched files

• If sequential: reset + clocking section in README

• If bus-facing: protocol cheat sheet in module doc

• If timing-critical: note expected critical path endpoint