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Course contents

  • RTL Foundations57
  • Combinational Design58
    • Combinational Timing Overview
    • Muxes, Decoders and Encoders
    • Arithmetic Blocks
    • Comparators and Shifters
    • Tri-State and Shared Buses
    • Latch Inference
    • Arithmetic Datapaths
      • Fixed-Point Contract
      • Width Growth
      • Rounding and Quantization
      • Saturation Policy
      • Divider Architectures
  • Sequential Design61
  • FSM & Control66
  • Timing & Clocking64
  • Reset & CDC58
  • Memory & Buses94
  • Advanced RTL60
  • Senior & Interview175
  • Glossary and Notation
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‹Arithmetic Datapaths
  1. Topics
  2. RTL Design
  3. Combinational Design
  4. Arithmetic Datapaths
  5. Saturation Policy

Part 2 · Combinational · Advanced

Saturation Policy

Clamp arithmetic overflow to representable limits instead of wrapping through the number line.

Why this matters

A large positive result that wraps to negative is catastrophic in signal processing and control. Saturation must compare the wide value before narrowing; once the result is narrowed it is too late.

After this lesson you can: round wide, clamp to the output range, then narrow, and compute the limits for a signed output of any width.

Wrapping is correct for addresses, counters, and modular arithmetic. Signal-processing and control quantities often need saturation because a large positive result wrapping negative is catastrophic.

For the sensor pipeline, saturation is applied after nearest-even rounding at the final Q1.15 boundary. Keeping the 42-bit accumulator intact until then avoids repeated clipping. The half-LSB error budget applies only to unclipped outputs; clipped results carry the saturation flag and are checked against the clamp policy, not that accuracy bound.

Round wide, clamp, then narrow

Quantization order: full precision, wide rounding, output-limit comparison, saturation, final narrowing.
Every comparison sees the widened rounded value; narrowing happens only after the range decision.

Step

Q2.2 input +1.50 -> signed Q2.0 output

Input code

0110 = 6, with F=2

Nearest-even to integer

6/4 = 1.5 -> four-bit signed code 0010 (+2), now with F=0

Output range

Two-bit signed codes -2 through +1

Clamp before narrowing

+2 exceeds +1: output code 01 (+1), saturation asserted if provided

Wrong: narrow first

+2 becomes 10 (-2); a subsequent two-bit range test cannot recover the lost sign

The range comparison is in output code units, after rescaling to the output's fractional-bit count. The running pipeline drops 15 low bits to move from F=30 to F=15, keeping the rounded code in wide signed storage. Sign-extend the signed output limits to that same width before comparing. For the Q1.15 output, +1.0 corresponds to rounded code 32768; it must clamp to 32767 (real value 1 - 2^-15), not wrap to -32768. Whether rounding or clipping sets a status flag is part of the interface contract.

Check yourself A wide nearest-even result is -3, but the target is signed two-bit Q2.0. What must be stored?

Clamp to -2, code 10, before narrowing. Simply taking the low two bits of -3 gives 01 (+1), the wrong sign.

design.sv
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// snippet: signed saturating add
logic signed [W-1:0] a, b, y;
logic signed [W:0] wide;
localparam logic signed [W-1:0] MAX = {1'b0, {(W-1){1'b1}}};
localparam logic signed [W-1:0] MIN = {1'b1, {(W-1){1'b0}}};

assign wide = {a[W-1], a} + {b[W-1], b};
always_comb begin
  if (wide > $signed(MAX))      y = MAX;
  else if (wide < $signed(MIN)) y = MIN;
  else                          y = wide[W-1:0];
end

Decision

Specify

Where to saturate

Each stage or only architectural output

Positive/negative limits

Signed or unsigned representable range

Flag

Pulse, sticky status, counter, or no report

Order

Round then saturate, or saturate at full precision

Common pitfall

Comparing a narrowed result to limits is too late: overflow has already wrapped. Compare the extended full-precision value, then clamp before narrowing.

Check yourself For signed W-bit saturation, what are the maximum and minimum codes?

Maximum is 0 followed by W-1 ones; minimum is 1 followed by W-1 zeros.

Remember

  • Wrap for addresses and counters. Saturate for signal and control values.

  • Compare the extended full-precision value with the limits, then narrow.

  • Signed limits: maximum is 0 followed by W-1 ones, minimum is 1 followed by W-1 zeros.

Rule of thumb: round wide, clamp, then narrow.

Keep going

  • Code lab: Build saturation logic

  • Interview: run a mock interview on this topic

Related topics

  • Pipelined MAC

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See also

  • Fixed-Point Contract
  • Width Growth