Architecture | Latency | Throughput | Area tendency | Use |
|---|---|---|---|---|
Combinational divider ( | Unclocked propagation delay; wrapper defines capture latency | One/cycle in a timed registered wrapper | Potentially large | Small widths or constant divisor |
Iterative restoring/non-restoring | About one bit per working cycle plus interface overhead | One result per ~W working cycles (+ interface overhead); not pipelined, so the next operation waits | Often smaller | Control and low-rate datapaths |
Fully pipelined | Many registered stages | One/cycle if unstalled | More parallel logic/registers | High-rate streams |
Reciprocal multiply | Pipeline dependent | Architecture dependent | Multiplier + approximation | DSP with bounded divisor range |
Every divider needs divide-by-zero behavior and signed corner handling. The signed minimum divided by -1 overflows in two's-complement because the positive result is not representable.
If the sensor pipeline adds programmable normalization, its divisor range and update rate decide the architecture: an iterative divider suits infrequent control updates, while a reciprocal pipeline suits one normalized sample per cycle.
Capture operands and signs.
Operate on magnitudes with an explicit iteration count.
Apply quotient and remainder signs.
Handle divide-by-zero and signed overflow before declaring valid.
For unsigned binary 1101 divided by 0011, start remainder R=0. At each step shift the next dividend bit into R; if that trial remainder is at least 3, subtract 3 and emit quotient bit 1, otherwise keep it and emit 0.
Read the columns left to right, one per clock step of a one-bit-per-cycle divider. A bar that reaches the dashed line subtracts.
Step 2: trial 2 x 1 + 1 = 3 equals the divisor, so it subtracts to R = 0 and emits a 1.
Steps 1, 3 and 4: the trial stays below 3, so the remainder is kept (restored) and the quotient bit is 0.
Result: the quotient bits read 0100 = 4 and the last R is 1.
Step / input bit | Trial remainder | Subtract 3? | New R | Quotient prefix |
|---|---|---|---|---|
1 / 1 | 2*0+1=1 | No | 1 | 0 |
2 / 1 | 2*1+1=3 | Yes | 0 | 01 |
3 / 0 | 2*0+0=0 | No | 0 | 010 |
4 / 1 | 2*0+1=1 | No | 1 | 0100 |
The result is quotient 0100=4 and remainder 1: 13=4*3+1, with 0<=R<3. A one-bit-per-cycle implementation needs four working steps here, plus whatever operand acceptance/completion overhead its interface specifies. An unrolled network performs the steps combinationally; a pipelined one trades registers and latency for initiation rate. Iteration count is not automatically the externally observed cycle latency.
Division by zero, and minimum-negative divided by -1, whose mathematical positive result exceeds the signed output range.