This course uses QI.F with I including the sign bit. Total width is I + F; therefore signed Q1.15 is a 16-bit value spanning -1 through 1 - 2^-15. Some texts exclude the sign bit and call the same layout Q0.15, so an interface specification must state its convention.

For the sensor pipeline, both inputs are signed Q1.15. The stored code x represents x / 2^15; the hardware still performs integer arithmetic.

Start with four bits

The bits 0110 do not say where the binary point belongs. Changing only the format label changes the interpreted value. To preserve +1.50 while increasing F from 2 to 3, first widen the signed code and then shift left: code 6 becomes code 12 (01100 in five-bit Q2.3), and 12 / 8 = 1.50. Four-bit Q1.3 cannot represent +1.50.

Alignment before addition is the same idea: +0.50 in Q2.2 has code 2, while +0.25 in Q2.3 has code 2. Adding raw codes gives 4 with an ambiguous scale. Convert the first operand to Q2.3 code 4, then add 4 + 2 = 6, which represents +0.75. Retain a growth bit for general addition.

Addition requires aligned binary points. Multiplication adds fractional bits: QI1.F1 times QI2.F2 produces a full result with F1+F2 fractional bits.

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// snippet: Q1.15 multiply, full precision then explicit rescale
logic signed [15:0] a_q15, b_q15;
logic signed [31:0] product_q30;
logic signed [15:0] result_q15;

assign product_q30 = a_q15 * b_q15;
assign result_q15  = product_q30 >>> 15;

This short scale illustration uses floor-and-wrap: arithmetic shift rounds toward negative infinity, and assignment retains only 16 bits. It is not the running design's final nearest-even-and-clamp boundary, implemented in the quantization lesson.

Related topics

• Width growth

• Number systems