Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • RTL Foundations36
  • Combinational Design25
    • Combinational Timing Overview
    • Muxes, Decoders and Encoders
    • Arithmetic Blocks
    • Comparators and Shifters
      • Magnitude Comparison
      • Barrel Shifter, Rotate and Arithmetic Shift
      • Mini Project: a Leading-Zero Counter and Normaliser
    • Tri-State and Shared Buses
    • Latch Inference
    • Arithmetic Datapaths
  • Sequential Design27
  • FSM & Control27
  • Timing & Clocking39
  • Reset & CDC34
  • Memory & Buses57
  • Advanced RTL28
  • Senior & Interview76
  • Glossary and Notation
Loading lesson

‹Comparators and Shifters
  1. Topics
  2. RTL Design
  3. Combinational Design
  4. Comparators and Shifters
  5. Barrel Shifter, Rotate and Arithmetic Shift

Part 2 · Combinational · Intermediate

Barrel Shifter, Rotate and Arithmetic Shift

A log-depth shifter for left, right, arithmetic and rotate shifts, with one stage per count bit.

On this page

    Why this matters

    A shift by a variable amount is a mux network. A 32-bit barrel shifter needs 5 stages, not 32, and the fill rule alone separates logical, arithmetic and rotate modes.

    After this lesson you can: build a log2 N stage barrel shifter, choose the fill for each mode, and state the delay and area cost.

    A shift by a variable amount

    Shifting by a constant is only wiring. Shifting by a variable amount needs a multiplexer network.

    A barrel shifter has one stage per bit of the shift count. Stage k passes the data through or shifts it by 2ᵏ positions, selected by bit k of the count.

    Any shift from 0 to N−1 is a sum of stage shifts, so log₂ N stages are enough.

    N may be 1 (a single-bit shifter): the shift-amount width is guarded as localparam int SW = (N > 1) ? $clog2(N) : 1; because $clog2(1) is 0, which would give a [-1:0] amount.

    Three cascaded shift stages controlled by the bits of the shift amount.
    An 8-bit shifter has 3 stages (1, 2, 4). A shift by 5 = 4 + 1 uses stages 0 and 2.

    Watch amt pick the stages: s1 always equals s0 because amt[1] stays 0. The diagram shows hex values.

    • Slot 1: amt is 0, so every stage passes the value through and y is 01.

    • Slot 2: amt is 1, so only stage 0 shifts and s0, s1 and y are 02.

    • Slot 3: amt is 4, so only stage 2 shifts and y is 10.

    • Slot 4: amt is 5, so stages 0 and 2 shift and y is 20.

    • Slot 5: new data 03 shifted by 5 gives s0 of 06 and y of 60.

    Shift modes

    Mode

    Operator

    Fills vacated bits with

    Typical use

    Logical left

    <<

    0

    Multiply by 2ᵏ, align

    Logical right

    >>

    0

    Unsigned divide, field extract

    Arithmetic right

    >>> (signed)

    Copies of the sign bit

    Signed divide by 2ᵏ, rounding toward −∞ (not toward 0 like /)

    Rotate left

    Schematic for 1 <= k < N: {d[N-k-1:0], d[N-1:N-k]} (k = 0 passes d through; variable k uses the shift/OR form in the testbench)

    Bits shifted out re-enter at the other end

    CRC, hashing, ciphers

    For an arithmetic right shift, each stage opens up 2ᵏ top bits. Each opened bit is a copy of the original sign bit. So one precomputed fill works for every stage.

    Two modes are missing on purpose.

    • No arithmetic-left mode. Left shifts always fill with 0, so logical and arithmetic left match.

    • No rotate-right mode. Rotate-right by k equals rotate-left by (N − k), so a left-only rotator is enough.

    Cost

    • Delay: log₂ N mux stages, not N. A 32-bit shifter has 5 stages.

    • Area: N·log₂ N 2:1 multiplexers. Doubling the width a little more than doubles the cost.

    • A shifter that supports only left shifts and uses a bit-reversal trick for right shifts can share the same stages, at the cost of two reversal layers.

    Common mistakes

    A common interview task is implementing a barrel shifter.

    • Stage per count bit: stage k shifts by 2ᵏ when amt[k] is set.

    • Fill decides the mode: 0 for logical, sign bit for arithmetic right, wraparound for rotate.

    • Cost is log₂ N stages, so a 32-bit shifter needs 5.

    Tip

    In RTL you normally write d << amt or d >>> amt and let synthesis build the barrel shifter. Write the structural version only when you need an unusual combination of modes (rotate with a mode input, say) or to understand the cost.

    Common pitfall

    >>> is arithmetic only if the operand is signed. On an unsigned vector it behaves like >>. Cast or declare the operand signed first.

    Check yourself Predict: rotate 8'b10000001 left by 1. What comes out?

    8'b00000011. The shifted-out 1 re-enters at the bottom.

    Check yourself Predict: arithmetic right shift of 8'b10000000 by 1. What comes out?

    8'b11000000. The sign bit copies into the opened top bit.

    Check yourself How many 2:1 mux stages does a 64-bit barrel shifter need, and what is the shift amount width?

    log₂ 64 = 6 stages, controlled by a 6-bit shift amount (0 to 63).

    Testbench

    The barrel shifter plus a testbench that checks every mode against the language operators.

    barrel.sv
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    20
    21
    22
    23
    24
    25
    26
    27
    28
    29
    module barrel #(parameter int N = 8) (   // N must be at least 1
      input  logic [N-1:0]         d,
      input  logic [(N > 1 ? $clog2(N) : 1)-1:0] amt,
      input  logic [1:0]           mode,     // 0: logical left, 1: logical right, 2: arithmetic right, 3: rotate left
      output logic [N-1:0]         y
    );
      // N = 1 guard ($clog2(1) is 0, so [$clog2(N)-1:0] would be [-1:0]).
      localparam int SW = (N > 1) ? $clog2(N) : 1;
      logic [N-1:0] s [SW+1];
      logic         fill;
    
      always_comb begin
        fill = (mode == 2'd2) ? d[N-1] : 1'b0;     // arithmetic right fills with the sign bit
        s[0] = d;
        for (int k = 0; k < SW; k++) begin
          if (amt[k]) begin
            case (mode)
              2'd0:    s[k+1] = s[k] << (1 << k);
              2'd1:    s[k+1] = s[k] >> (1 << k);
              2'd2:    s[k+1] = (s[k] >> (1 << k)) | ({N{fill}} << (N - (1 << k)));
              default: s[k+1] = (s[k] << (1 << k)) | (s[k] >> (N - (1 << k)));
            endcase
          end else begin
            s[k+1] = s[k];
          end
        end
        y = s[SW];
      end
    endmodule
    

    Remember

    • Stage k shifts by 2^k when amt[k] is set, so log2 N stages cover every shift from 0 to N-1.

    • Fill decides the mode: 0 for logical, the sign bit for arithmetic right, wraparound for rotate.

    • Delay is log2 N mux stages; area is about N * log2 N muxes. >>> is arithmetic only on a signed operand.

    Keep going

    • Practice: A barrel shifter with left, right and rotate modes

    • Code lab: Build a barrel shift left

    • Interview: run a mock interview on this topic

    Related topics

    • Shift and arithmetic intent

    • Mini project: a leading-zero counter and normaliser

    Previous

    49 / 350

    Next: Mini Project: a Leading-Zero Counter and Normaliser

    Up next

    Up nextMini Project: a Leading-Zero Counter and Normaliser

    Sign in to save progress

    Practice this lessonReport an error
    clkd13amt0145s012126s112126y12102060
    Logical-left shift by 0, 1, 4 and 5 through three stages