Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • RTL Foundations36
  • Combinational Design25
  • Sequential Design27
  • FSM & Control27
    • Controller and Datapath
    • Moore vs Mealy
      • Behavioral Difference
      • Side-by-Side: A Sequence Detector
      • Registered Mealy Outputs
      • Choosing and Verifying
    • State Encoding
    • Multi-Cycle Sequencers
    • UART Transmitter
    • Memory Controller
  • Timing & Clocking39
  • Reset & CDC34
  • Memory & Buses57
  • Advanced RTL28
  • Senior & Interview76
  • Glossary and Notation
Loading lesson

‹Moore vs Mealy
  1. Topics
  2. RTL Design
  3. FSM & Control
  4. Moore vs Mealy
  5. Behavioral Difference

Part 4 · FSM & Control · Intermediate

Behavioral Difference

The shown two-ones detectors differ by one cycle at just-before-edge observations.

On this page

    Why this matters

    Mealy raises its output in the cycle the second 1 arrives and Moore one observation later. Mix them up and a testbench or a downstream block samples a cycle early or late.

    After this lesson you can: predict the output timing of a Moore and a Mealy detector for the same input, and say why they are equivalent in function.

    Outputs one cycle apart in this example

    Take the task “raise y when the input has been 1 for two consecutive cycles”. In the two implementations below, at just-before-rising-edge observations, Mealy raises y in the cycle the second 1 arrives and Moore reports it at the following observation.

    A Mealy machine sees the input together with the state that records one earlier 1, so it detects the second 1 at once. A Moore machine sees only the state, so it enters its “two ones seen” state at the next clock edge.

    The two y rows show the same detections one cycle apart.

    • `clk`: marks sampling just before each rising edge.

    • `x`: carries isolated and paired 1s that form the detections.

    • `y` (Mealy): rises in the same cycle as each second 1.

    • `y` (Moore): repeats each detection one cycle later.

    Timing and state cost

    The table describes these detectors. The Mealy decision is visible earlier because it uses a combinational path, which does not by itself allow a faster clock.

    Moore

    Mealy

    Response to an input change

    After the next clock edge

    Immediately (combinational path from input to output)

    Output stability inside a cycle

    Stable once state/decode settle; register the output if glitch freedom is required

    Can glitch or change mid-cycle if inputs change

    Number of states for the same job

    Usually equal or one more

    Usually fewer

    Output timing path

    Register → output logic → port (clock-to-out)

    Input port → logic → output port (input-to-output)

    Common mistakes

    Common pitfall

    A Mealy output that feeds another block is a combinational path from your input to their logic. Chain two Mealy machines and you can end up with a long, hard-to-constrain path across the design. Register the output, or use Moore at block boundaries.

    The two machines are equivalent in function: the same input stream always produces the same sequence of detections. They differ only in when, relative to the clock, the output is visible.

    Check yourself On the waveform, why does the Moore output go high at cycle 8 as well as at cycle 7?

    The input stays at 1 through cycles 5, 6 and 7. Overlapping pairs (5,6) and (6,7) are both detected. The Moore machine sits in its “two ones seen” state for cycles 7 and 8, one cycle behind the Mealy detections.

    Remember

    • A Mealy output uses the state and the live input, so it responds in the same cycle.

    • A Moore output uses the state only, so it follows the clock edge that enters the state.

    • A Mealy output feeding another block is a combinational path from your input to their logic.

    How this was checked

    The one-observation gap holds for these state meanings and output expressions. It is not a universal latency law.

    Keep going

    • Practice: Types of FSMs and their difference

    • Practice: How outputs are generated in Moore FSMs

    • Interview: run a mock interview on this topic

    Related topics

    • Side-by-side example

    Previous

    95 / 350

    Next: Side-by-Side: A Sequence Detector

    Up next

    Up nextSide-by-Side: A Sequence Detector

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Registered Mealy Outputs
    • Choosing and Verifying
    Detect two consecutive 1s, sampled just before each rising edgeclkxy (Moore)y (Mealy)
    At the just-before-edge observations, Mealy y is high in cycles 3, 6 and 7; Moore y is high in cycles 4, 7 and 8. Adjacent detections keep y high across consecutive observations. The trace in the next lesson follows these same input samples.