A Mealy output is a combinational function of the inputs. If it drives another block, or leaves the chip, that path is exposed.
To create a flop-driven boundary, register the output: capture the Mealy decision at a rising edge. With reset inactive, the output holds between active edges after clock-to-Q settles. The asynchronous reset shown below can change it between edges.
For these two-ones detectors, registration moves the decision from before the capture edge to after it. At the just-before-edge observations used in the preceding lesson, registered Mealy and Moore both report one observation later than plain Mealy. Other state/output contracts can have different latency.
The table compares the shown detectors at just-before-edge observations. Registration costs one output flop and one observation interval.
Plain Mealy | Registered Mealy | Moore | |
|---|---|---|---|
Input → output path | Combinational | None (flop in between) | None |
Observation delay for these detectors | 0 intervals | 1 interval | 1 interval |
State bits | Fewest | Fewest + 1 output flop | Often more |
Between-edge stability, reset inactive | Input changes propagate | Flop holds after clock-to-Q settles | Only with a justified hazard-free decode or registered output |
Each clock cycle takes two slots here: one just after the rising edge (clk high) and one just after the falling edge (clk low). The cycles are numbered 0 to 5.
Cycles 2 and 3: y_mealy reports the two pairs of ones as soon as the second 1 of each pair is on x.
Cycle 2, low slot: x dips to 0 between edges and y_mealy drops with it. y_reg does not move: it changes only at rising edges.
Cycles 3 and 4: y_reg and y_moore report the same two detections, one cycle after y_mealy, and the two lanes are identical. That is the 0 versus 1 interval in the table.
A registered Mealy output is, in effect, a Moore machine whose state includes the output bit. That is a useful view: you are free to pick whichever description is easier to read.
The listing checks 3000 captured decisions and one input perturbation between edges per iteration with reset inactive, then checks asynchronous reset separately.
module det_mealy_reg (input logic clk, rst_n, x, output logic y);
logic prev; // state: the previous sample was 1
logic y_next;
assign y_next = prev && x; // the Mealy decision (combinational)
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) begin prev <= 1'b0; y <= 1'b0; end
else begin prev <= x; y <= y_next; end // y is now a flop output
endmodule
y one cycle after the plain Mealy version. Where did the extra cycle come from?From the output flip-flop. The decision is computed in the cycle the input arrives, but it is only captured, and visible, after the following clock edge.
The testbench checks 3000 captured decisions with one input perturbation between edges per iteration, then checks asynchronous reset separately. It is a bounded functional check, not physical glitch or CDC signoff.