Same spec, two machines

Spec: y indicates that the last two input samples (the current one and the one before) were both 1. The two codings differ in the state meaning and in the output expression.

Read the output from the right place

Trace the same samples as the waveform

Use the just-before-rising-edge observation point from the behavioral-difference waveform. The input has settled, but the state register has not yet accepted that sample. Both machines start in S0 after reset. The Mealy and Moore columns show state before / y before. Moore after is the state once the upcoming edge's update settles; its output then follows that new state.

At cycle 3, Mealy sees S1 together with x=1 and asserts y before the edge. Moore still occupies S1 and reports 0; that edge enters S11, so the following observation reports 1. Cycles 6 and 7 detect overlapping pairs, producing the two consecutive Moore hits at cycles 7 and 8. The one-cycle relationship is for this implementation and observation convention, not a universal latency rule for every Moore/Mealy design.

Reading the output expressions

y = (state == S1) && x has two parts. The first (state == S1) is memory (“the previous sample was 1”), and the second (x) is the live input.

Remove && x and the output signals only “the previous sample was 1”, which is a different, wrong spec.

Common mistakes

Testbench

The listing below checks both machines against one reference model.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

module det_moore (input logic clk, rst_n, x, output logic y);
  typedef enum logic [1:0] {S0, S1, S11} state_t;
  state_t state, next;

  always_comb begin
    next = state;
    unique case (state)
      S0:      if (x)  next = S1;
      S1:      if (x)  next = S11; else next = S0;
      S11:     if (!x) next = S0;
      default: next = S0;
    endcase
  end

  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) state <= S0;
    else        state <= next;

  assign y = (state == S11);          // Moore: state only
endmodule

module det_mealy (input logic clk, rst_n, x, output logic y);
  typedef enum logic {S0, S1} state_t;  // S1 = the previous sample was 1
  state_t state;

  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n)  state <= S0;
    else if (x)  state <= S1;
    else         state <= S0;

  assign y = (state == S1) && x;       // Mealy: state AND input
endmodule

Related topics

• Registered Mealy outputs