Without scan, many faults remain hidden because functional paths are too deep or require impractical input sequences.
A 4-bit counter stands in for that depth. Reaching state 15 from reset takes 15 clock edges functionally, and the count grows exponentially with state width.
Automatic test-pattern generation treats each capture cycle as combinational logic between scan flops. Three properties make that work.
Property | Question it answers | RTL consequence |
|---|---|---|
Controllability | Can the tool drive an internal node to 0 and 1? | Every flop reachable from scan-in |
Observability | Can a node effect reach scan-out or a primary output? | Key nodes captured into scan-visible flops |
Deterministic test mode | Are clocks, resets, and constraints predictable while shifting? | The integration checklist in the next lessons |
Read the chain left to right: the coloured wire is the scan path and the dark wires are functional logic.
Each flop has a mux in front of it. scan_en = 1 takes the previous flop, scan_en = 0 takes the functional input.
Shifting in 0,0,1,1 puts the first bit in q3, so the chain reads q3 q2 q1 q0 = 0 0 1 1.
The capture edge loads n = q1 & q0 = 1 into q3. Shifting out then shows q3 first.
The lower panel counts edges: 15 to count up to state 15, 4 to load it directly.
Worked fault destination: the four-flop chain below uses q0-to-q3 serial order. Load 0011, activate a stuck-at-0 defect on n = q[1] & q[0], capture n into q[3], then read q[3] first. The parallel-load counter remains an access stand-in; the next lesson adds this fault experiment to the serial chain.
Scan does not change the functional design. It adds a second way to reach the same state.
Task | Without scan | With scan |
|---|---|---|
Reach a deep state | Run a long functional sequence | Shift the state in directly |
Observe a deep node | Propagate its effect to a pin | Capture it and shift it out |
Generate patterns | Sequential search over many cycles | Combinational search per capture cycle |
Reaching any one of a million states can need a long, exact input sequence. The tool must search cycle by cycle instead of loading the state directly.
Untestable or unconstrained logic, not the chain. Check tied-off modes, undriven inputs, and X sources before suspecting the stitching.
A 4-bit counter with a parallel load stands in for scan access. The testbench counts functionally, then loads directly.
`timescale 1ns/1ps
module deep_state (
input logic clk,
input logic rst_n,
input logic load_i,
input logic [3:0] load_val_i,
output logic [3:0] q_o
);
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) q_o <= 4'd0;
else if (load_i) q_o <= load_val_i;
else q_o <= q_o + 4'd1;
end
endmodule