Metric | Meaning | Unit | Pipeline effect |
|---|---|---|---|
Latency | Time from an item entering to its result leaving | Cycles (or ns) | Grows by one cycle per added stage |
Throughput | Results completed per unit time | Results / cycle (or per second) | Up to 1 result per cycle once full |
Without pipelining, a block with total delay D needs a period near D plus register overhead. It completes one item per clock.
Cut into S balanced stages, the period falls toward D/S plus overhead. Each item then takes S cycles to emerge.
Stages S | Clock period (D = 6 ns, t_reg = 0.3 ns) | Frequency | Latency (ns) |
|---|---|---|---|
1 | 6.3 ns | 159 MHz | 6.3 |
2 | 3.3 ns | 303 MHz | 6.6 |
3 | 2.3 ns | 435 MHz | 6.9 |
6 | 1.3 ns | 769 MHz | 7.8 |
Latency in time barely changes, and even grows slightly from register overhead. The gain is clock frequency and throughput over streams of items.
Read it left to right: the top two data lanes are the input, the bottom two are the output. Each slot is one clock cycle.
Item A enters in slot 0 and leaves in slot 3, so latency is S = 3 cycles.
From slot 3 to slot 8 out_valid stays high: one result per cycle, which is the full throughput.
Input stops after slot 5, but F is still inside the pipe, so the output keeps going until slot 8 (draining).
out_data shows 0 while out_valid is low; the value is not meaningful there.
Extra registers: S−1 ranks of area, power, and clock load.
Later results: S cycles of latency, felt in feedback loops and control decisions.
Feedback loops: a result needed before the next input cannot simply gain stages.
Dependencies across stages need stalls or forwarding.
Balance: the slowest stage sets the clock, so uneven stages waste the gain.
T ≈ 4.8/4 + 0.2 = 1.4 ns, so about 714 MHz. Latency = 4 × 1.4 = 5.6 ns, longer than the unpipelined 5.0 ns, with about 5.0/1.4 ≈ 3.57× the results per ns, below the ideal 4× because of register overhead.
A delay pipeline fed a new item every cycle, checked for one result per cycle and exactly S cycles from each accepted input to downstream consumption. The monitor records acceptance and consumes outputs before rising-edge NBA updates, matching a downstream register's view. The module requires S >= 1 (an array of zero ranks has no output to read); an elaboration-time guard reports a clear error otherwise.
module delay_pipe #(parameter int S = 3, parameter int W = 8) ( // S >= 1
input logic clk, rst_n,
input logic in_valid,
input logic [W-1:0] in_data,
output logic out_valid,
output logic [W-1:0] out_data
);
if (S < 1) begin : g_s_check
$error("delay_pipe: S must be at least 1");
end
logic v [S];
logic [W-1:0] d [S];
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) for (int i = 0; i < S; i++) v[i] <= 1'b0;
else begin
v[0] <= in_valid;
for (int i = 1; i < S; i++) v[i] <= v[i-1];
end
always_ff @(posedge clk) begin
d[0] <= in_data;
for (int i = 1; i < S; i++) d[i] <= d[i-1];
end
assign out_valid = v[S-1];
assign out_data = d[S-1];
endmodule