Read each box as artifact over owner. The table gives what the RTL owner still checks in each one.
Artifact | Primary owner | RTL owner verifies |
|---|---|---|
RTL + parameters | RTL | Configuration is legal and traceable |
SDC clocks/exceptions | STA with RTL input | Generated clocks and exceptions match architecture |
CDC/RDC constraints | CDC/RTL | Crossing structures and waivers match implementation |
UPF | Low-power | Ports, domains, isolation and retention match RTL |
DFT protocol | DFT | Test clocks/resets/modes are controllable |
Synthesis setup | Synthesis/CAD | Top, files, defines, black boxes and libraries are correct |
For the checksum pipeline change, the RTL owner updates the latency contract and handoff manifest; STA reviews the new path boundary; verification adjusts transaction alignment; and the LEC owner selects a sequential comparison strategy rather than expecting identical internal registers.
Contract field | C0 baseline | C1 candidate / owner |
|---|---|---|
Function | sum=(w0+w1+w2+w3) modulo 65536; four unsigned 16-bit words and tag | Same function; RTL owns bit width and overflow semantics |
Acceptance | Every rising edge with in_valid and reset inactive; no READY | Same; verification owns ordered tag scoreboard; sink always accepts |
Availability for input accepted at E0 | sum/tag/valid available after E0; clocked sink consumes at E1 | Pair sums/tag/valid after E0; final sum/tag/valid after E1; sink consumes at E2 |
Throughput | One accepted item per edge | One per edge; architecture approves added cycle |
Reset | Asynchronous assertion clears valid; synchronous release in this clock domain | Clears both valid stages; pending items cancelled, never delivered later |
State delta | One output stage | One additional partial-sum stage; LEC owner aligns external transactions |
Manifest C1 names C0 as rollback, fixes top/parameters/defines, SDC and UPF revisions, library/RC/tool versions, activity stimulus and seed set {11,29,47}. Only the pipeline RTL changes. STA owns new endpoints and all timing views; physical design owns placement/route checks; verification and architecture review the latency and reset cancellation contract.
Every waiver links to a reviewed reason and expiry condition.
Every black box has a timing/functional model or an explicit risk owner.
Every generated artifact records source revision and tool version.
Interface latency, reset, clock, power, and test-mode assumptions are part of the handoff.
STA owns the constraint flow, while RTL owns exposing and documenting the divide relationship. Both review that the constrained object and functional mode match.
The checksum dossier is entirely illustrative and unexecuted: its invented planning values are not measured results or signoff evidence.