Freeze and reproduce the failing baseline.
Classify root cause: RTL, constraint, library, physical, CDC, or environment.
Choose the smallest change that fixes the cause, not only the symptom.
Run functional, equivalence, lint, CDC/RDC, synthesis, STA, power, DFT, and physical checks affected by the change.
Compare all modes/corners and neighboring paths, not only the original violation.
Record change, evidence, residual risks, waivers, approvals, and rollback point.
The checksum change is released only after latency-aware regression, sequential equivalence, all-corner setup and hold, power, congestion, and downstream interface checks agree. The release note records the old and new pipeline latency and provides a rollback revision.
Disposition | Dossier decision |
|---|---|
Keep | Not justified: setup gain alone cannot waive failed hold/power budgets |
Revise C1 (selected) | Physical/STA owners investigate new short paths and hold repair; RTL/power owners investigate added clock load; architecture retains the approved extra cycle |
Reject / rollback to C0 | If repairs cannot meet all budgets across paired seeds and modes, reject C1 and reopen baseline setup closure; C0 itself is not signoff clean |
Release status | Blocked in this hypothetical dossier; formal, regression and physical evidence remain unexecuted obligations |
Any C2 revision needs a fresh controlled comparison against C0/C1, latency-aware regression, sequential equivalence and all affected signoff views. Attach report revisions, waiver owners/expiry, downstream latency approval and rollback manifest before release; do not turn this illustrative decision into a claimed passing run.
Change | Minimum regression |
|---|---|
Combinational RTL | Sim/formal, lint, LEC, synth, all timing views, power |
Pipeline stage | Architecture latency, scoreboard, LEC strategy, CDC, STA |
Reset/clock | Reset tests, CDC/RDC, STA clocks, DFT, low power |
Constraint | Constraint audit, unconstrained paths, all modes/corners |
Gate ECO | LEC, STA setup/hold, physical DRC, power and affected tests |
Sizing, buffering, or restructuring that improves a slow path can create a new fast path or alter clock/data balance, causing hold failures.
The release decision is illustrative and unexecuted. Any revision needs a fresh controlled comparison before release; it is not a claimed passing run.