Devices & Building-Block Circuits: Tricky Q&A

[INT][ANALOG][DEVICES-AND-CIRCUITS]

Q: Why does an NMOS that is a great digital switch become a poor linear analog element near the rail?

A:
As the signal approaches the gate voltage, VGS overdrive shrinks and the device moves toward weak conduction, so on-resistance rises and becomes strongly signal-dependent. That creates distortion, gain compression, and slower settling even though logic-level toggling still appears correct. In analog paths, headroom and region control matter more than binary on or off state.

FOLLOW-UP TRAP: Assuming digital pass or fail behavior implies constant low resistance over the full analog swing.

[INT][ANALOG][DEVICES-AND-CIRCUITS]

Q: What is the subtle failure mode when a current mirror looks ratio-correct at nominal but breaks in silicon corners?

A:
Nominal ratio checks can hide compliance and output-resistance sensitivity, so mirrored current collapses when VDS headroom is reduced by corner, load, or supply shift. Mismatch and temperature effects then amplify absolute error, moving downstream stages out of their intended operating region. Robust mirror design therefore needs compliance sweeps and mismatch-aware budgeting, not only ideal ratio matching.

FOLLOW-UP TRAP: Treating mirror accuracy as only a geometry ratio problem at TT corner.

[INT][ANALOG][DEVICES-AND-CIRCUITS]

Q: Why can a closed-loop op-amp design meet DC gain targets yet still oscillate in system bring-up?

A:
DC gain targets say little about loop phase at crossover. Parasitic poles from load capacitance, routing, or package interactions can erode phase margin after integration, especially when compensation was tuned in isolation. The loop then rings or oscillates even though small-signal DC error looked acceptable in pre-integration simulation.

FOLLOW-UP TRAP: Equating high open-loop gain with guaranteed closed-loop stability.

[INT][ANALOG][DEVICES-AND-CIRCUITS]

Q: How is comparator metastability similar to digital synchronizer uncertainty, and what extra analog pitfall is common?

A:
Both involve prolonged resolution time when the input differential is near zero at the decision instant, creating cycle-to-cycle timing uncertainty. Comparators add analog-specific pitfalls: input kickback and offset can shift the effective decision point and perturb the source itself. That means timing and threshold integrity must be co-designed, not treated as separate concerns.

FOLLOW-UP TRAP: Thinking comparator errors are only timing-related and independent of front-end analog interaction.

SYMPTOM -> ANALOG MECHANISM -> EVIDENCE -> OWNER ACTION -> VALIDATION

CIRCUIT REASONING FLOW

device region -> small-signal model -> loop behavior -> integration risk