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Course contents

  • How to Use This Course
  • Reading Paths
  • Glossary
  • Metrics Reference
  • Formal Cheat Sheet
  • Formal Foundations19
  • Properties and SVA16
  • Property Development and Constraints19
  • Proof Engines and Convergence23
  • Formal Applications20
  • Equivalence Checking14
  • Formal Coverage and Signoff15
  • Methodology and Debug13
  • Interview Prep15
  • Capstone: A Chip-Block Verification Lab24
    • The Brief
    • Stage 1: FIFO and Handshake
      • Stage 1 FIFO Property Set
      • Stage 1 Bridge and the Assumption Contract
      • Stage 1 Covers and Mutants
    • Stage 2: Registers and Arbiter
    • Stage 3: Pipeline and Equivalence
    • Stage 4: Induction and Signoff
    • Solutions
    • Appendix: Run It Yourself on an Open-Source Flow
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←Capstone: A Chip-Block Verification Lab
  1. Topics
  2. Formal Verification
  3. Capstone: A Chip-Block Verification Lab
  4. Stage 1: FIFO and Handshake

Part 10 of 10Part 10 of 10/Capstone: A Chip-Block Verification LabAll levels

Stage 1: FIFO and Handshake

Prove the FIFO and the bridge, find each planted fault from its symptom, and close the stage with covers and mutants.

  • 3topics
  • 3lessons

Stage 1 covers the two storage designs: the FIFO that must never lose or reorder a word, and the bridge stage that must never lose a word under backpressure. Both are safety work and close in full with helper assertions. Each lesson gives you the design, the property set already written, a deliverable and a pass criterion; the causes of the eight planted faults are in the Solutions topic after stage 4.

Lesson

After it you can...

Stage 1 FIFO Property Set

Prove the FIFO set, locate five planted faults by counterexample, and file the rows.

Stage 1 Bridge and the Assumption Contract

Prove the bridge with every input free, and judge a proposed input rule.

Stage 1 Covers and Mutants

Build the mutation table, find survivors under reduced property sets, and file the covers.

Suggested order: top to bottom. The FIFO lesson fixes the ledger habit; the bridge lesson adds the assumption register; the covers lesson tests both. Do not start stage 2 until your stage 1 package passes the engine.

A proof of the good design is followed by a run of each variant to find the failing property. Rows are filed citing the runs, covers and the mutation table follow, and the engine checks the package.
The stage 1 loop: prove the good design, break it with each variant, file rows, add covers and the mutation table, then run the engine.
Check yourself Why does this stage file no bounded rows for the good designs?

Both designs close in full with their helper assertions, so a bounded row would be an unfinished proof. Bounded rows appear only where a lab argument justifies them.

Related topics

  • Back: The Lab Harness and Engine

  • Earlier: Abstraction and Complexity

  • Formal Glossary

PreviousNext: Stage 1 FIFO Property Set

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See also

  • The Brief
  • Stage 2: Registers and Arbiter
  • Stage 3: Pipeline and Equivalence