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Course contents

  • How to Use This Course
  • Reading Paths
  • Glossary
  • Metrics Reference
  • Formal Cheat Sheet
  • Formal Foundations19
  • Properties and SVA16
  • Property Development and Constraints19
  • Proof Engines and Convergence23
  • Formal Applications20
  • Equivalence Checking14
  • Formal Coverage and Signoff15
  • Methodology and Debug13
  • Interview Prep15
  • Capstone: A Chip-Block Verification Lab24
    • The Brief
    • Stage 1: FIFO and Handshake
    • Stage 2: Registers and Arbiter
    • Stage 3: Pipeline and Equivalence
      • Stage 3 Pipeline Latency Properties
      • Stage 3 Retimed Twin Equivalence
      • Stage 3 ECO and the Intended Difference
    • Stage 4: Induction and Signoff
    • Solutions
    • Appendix: Run It Yourself on an Open-Source Flow
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←Capstone: A Chip-Block Verification Lab
  1. Topics
  2. Formal Verification
  3. Capstone: A Chip-Block Verification Lab
  4. Stage 3: Pipeline and Equivalence

Part 10 of 10Part 10 of 10/Capstone: A Chip-Block Verification LabAll levels

Stage 3: Pipeline and Equivalence

Prove the pipeline latency, match the retimed twin in a miter, and scope one change to the arbiter.

  • 3topics
  • 3lessons

Stage 3 moves from what one design does to whether two designs agree. The pipeline lesson pins latency and the reset rule on the reference. The miter lesson proves the retimed twin equal, finds the planted twin fault, and measures the induction window with and without a helper. The last lesson scopes one intended change and proves everything outside it untouched. Causes are in the Solutions topic after stage 4.

Lesson

After it you can...

Stage 3 Pipeline Latency Properties

Prove the latency-3 result, find the smallest induction window, and write your own mutants.

Stage 3 Retimed Twin Equivalence

Prove miter equivalence, find the twin fault, and compare the windows with and without the helper.

Stage 3 ECO and the Intended Difference

Exhibit an intended difference and prove equivalence outside it.

Suggested order: top to bottom. Latency first, because the miter says the twins agree, not that either is right; the twin next; the ECO last, because it reuses the miter idea with a changed revision.

A reference pipeline whose latency is proved and a retimed twin feed a miter. The miter asserts that the outputs are equal in every cycle. The ECO lesson reuses the same idea with a changed revision and a scoped claim.
The stage 3 structure: the proved reference and the twin feed one miter that asserts equal outputs; the ECO lesson reuses it with a scoped claim.
Check yourself Why must the reference meet its own specification before the miter means anything?

Equal outputs prove the implementations agree, not that either is right: two copies of the same fault agree perfectly. The latency proof is the correctness half; the miter is the agreement half.

Related topics

  • Back: Stage 2 Reset Determinism and Connectivity

  • Earlier: Sequential Equivalence

  • Formal Glossary

PreviousNext: Stage 3 Pipeline Latency Properties

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See also

  • The Brief
  • Stage 1: FIFO and Handshake
  • Stage 2: Registers and Arbiter