Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • Reading Paths
  • Concept Map
  • How to Read the Diagrams
  • Part 0: What Is a Protocol?10
  • Part 1: Timing and Clocking11
  • Part 2: Encoding and Framing12
  • Part 3: Handshakes13
  • Part 4: Flow Control17
  • Part 5: Transactions19
  • Part 6: Concurrency and Performance17
  • Part 7: Ordering13
  • Part 8: Sharing and Arbitration12
  • Part 9: Deadlock and Liveness13
    • Deadlock, Livelock and Starvation
    • Deadlock Conditions and Graphs
    • Channel Dependencies
    • Message-Dependent Deadlock
    • The Consumption Assumption
    • Routing Deadlock
    • Pre-allocation or Retry
    • Retry Livelock
    • Timeouts and Watchdogs
    • Hang Debug
    • Proving Deadlock Freedom
    • Protocols Compared: Deadlock and Liveness
    • Drills: Deadlock and Liveness
  • Part 10: Reliability and Recovery20
  • Part 11: Bring-Up and Link Management10
  • Part 12: Power8
  • Part 13: Shared State and Coherence9
  • Part 14: Security and Isolation7
  • Part 15: Specifying and Verifying11
  • Part 16: Protocols Dissected17
  • Part 17: Capstones5
  • Part 18: Interview Preparation6
Loading lesson

‹Part 9: Deadlock and Liveness
  1. Topics
  2. First Principles of Hardware Protocols
  3. Part 9: Deadlock and Liveness
  4. Protocols Compared: Deadlock and Liveness

Part 9 · Deadlock and Liveness · All levels

Protocols Compared: Deadlock and Liveness

How AXI, PCI Express, AMBA CHI, on-chip networks and DCLink avoid deadlock and livelock: dependency rules, message classes, consumption, routing, retry and timeouts.

On this page

    Read across for one protocol; read down to see how each removes the same cycles in a different way.

    Deadlock avoidance, side by side

    AXI

    PCI Express

    AMBA CHI

    On-chip network

    DCLink

    Channel dependency rules

    Valid must not wait for ready; BVALID only after address and last data

    Ordering table: posted and completions pass blocked non-posted

    Per-channel rules

    Per-VC flow control

    Valid/ready rule (step 2)

    Message classes

    Separate request and response channels

    Posted, non-posted, completion credits

    Separate request, response, snoop and data channels

    VCs per message class

    Request and completion buffers (step 8)

    Consumption

    Managers must eventually accept responses

    Endpoints advertise infinite completion credits

    Responses always sunk

    Network interfaces sink responses

    Completions always accepted

    Routing deadlock

    —

    Tree topology: no cycles

    Fabric-specific

    XY routing, or datelines and escape VCs

    Point to point

    Full target

    Back-pressure (ready low)

    Credits: never sent without room

    Retry plus protocol credit

    Back-pressure per VC

    Credits

    Timeouts

    Implementation-defined

    Completion timeouts, 50 µs to 64 s

    Implementation-defined

    Implementation-defined

    —

    What the table shows

    • Every protocol separates requests from responses and requires responses to be consumed: message-dependent deadlock is universal.

    • Routing deadlock is avoided by topology or routing rules: trees have no cycles; meshes use XY; rings use datelines.

    • A full target is handled by back-pressure, pre-allocation (credits) or retry with a guarantee, never by plain retry at scale.

    Where each idea is explained

    • 9.2 Deadlock Conditions and Graphs

    • 9.3 Channel Dependencies

    • 9.4 Message-Dependent Deadlock

    • 9.5 The Consumption Assumption

    • 9.6 Routing Deadlock

    • 9.7 Pre-allocation or Retry

    • 9.9 Timeouts and Watchdogs

    Tip

    For any fabric, list every buffering resource and every "may wait for" between them, and show the list can be numbered so that every wait goes upward.

    Keep going

    Next: Drills: Deadlock and Liveness. Interview questions, a whiteboard exercise and a ten-question checkpoint for Part 9.

    Related topics

    • Part 9 overview: Deadlock and Liveness

    • Course hub

    Previous

    140 / 234

    Next: Drills: Deadlock and Liveness

    Up next

    Up nextDrills: Deadlock and Liveness

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Deadlock, Livelock and Starvation
    • Deadlock Conditions and Graphs
    • Channel Dependencies