Read across for one protocol; read down to see how differently the same sharing questions are answered.
I2C | CAN | AHB | AXI interconnect | PCI Express | On-chip network | |
|---|---|---|---|---|---|---|
Who arbitrates | The wire (wired-AND) | The wire (dominant bits) | A central arbiter | Arbiters per target port | Each switch output; endpoints are point-to-point | Each router output |
Priority comes from | Address bits | Identifier bits | Arbiter policy | Policy plus AxQOS | Traffic class, VC arbitration | Class, VC, age |
Granularity | Whole transfer | Whole frame | Per transfer (locked sequences hold) | Per transaction; read data per beat across IDs | Per packet | Per packet or per flit across VCs |
Isolation between classes | None | By identifier priority | None | Independent channels | Virtual channels per traffic class | Virtual channels per message class |
Routing | — | — | Address decode | Address decode | Address and ID routing through switches | Usually XY in meshes |
Slow, shared wires arbitrate on the wire itself; fast on-chip fabrics use central or per-port arbiters.
Priority is either built into the message (I2C, CAN) or carried as a field (AxQOS, traffic class).
Isolation needs separate buffers: virtual channels in PCIe and networks-on-chip, independent channels in AXI.