SoC Integration · All levels
Bus Fabrics & Interconnect: Tricky Q&A
Senior interview and review questions for Bus Fabrics & Interconnect.
Section Q&A bank
Use these drills after completing all topics in Bus Fabrics & Interconnect. Answer with baseline, boundary, owner, metric, artifact, and regression scope.
Why does average bandwidth hide real SoC pain?
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[INT][SOC][BUS-FABRICS]
Q: Why does average bandwidth hide real SoC pain?
A:
User-visible failures usually come from p99 latency tail and starvation under mixed traffic, not average throughput.
FOLLOW-UP TRAP: Declaring success from peak synthetic benchmark numbers.What breaks AXI/ACE integration most often?
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[INT][SOC][BUS-FABRICS]
Q: What breaks AXI/ACE integration most often?
A:
ID/order/attribute corruption across bridges or adapters, especially under outstanding transactions.
FOLLOW-UP TRAP: Debugging only one channel in isolation.How do you isolate a contention root cause?
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[INT][SOC][BUS-FABRICS]
Q: How do you isolate a contention root cause?
A:
Pin one hotspot flow, map arbitration and VC behavior, then prove which policy causes head-of-line blocking.
FOLLOW-UP TRAP: Immediately increasing buffer sizes globally.Q&A drill guide
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BASELINE -> OWNER -> CONTRACT -> METRIC -> FIX -> REGRESSIONSketch while answering
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FABRIC FLOW
masters -> routers/VCs -> slaves + memoryKey takeaways
State baseline manifest and owner with every closure metric.
Run cross-domain regression after every top-level fix.
Common pitfalls
Comparing results across different manifests.
Unowned issues slipping through review cycles.
Waiving risks without expiry and validation plan.