Bump planning, package SI/PI contracts, chip-package co-design, and package-related bring-up failure analysis.
Start with the topic hub to learn the integration contract.
Use mechanism and reports pages to connect contract to metrics.
Use debug and worked-example pages for war-room readiness.
Close with checklist and PPA impact before closure signoff.
bump-map-and-escape-planning/ — Bump Map & Escape Planning
package-si-pi-contracts/ — Package SI/PI Contracts
chip-package-io-co-design/ — Chip-Package I/O Co-design
package-bringup-and-failures/ — Package Bring-up & Failures
Package assumptions must be treated as first-class chip constraints.
PACKAGE CO-DESIGN
die io <-> package routing <-> board constraintsPACKAGE RISK MIX
SI margin █████
power integrity ████
lane mapping ███bump map revision log
SI/PI margin report
IO co-design checklist
package bring-up failures
Link degradation on product board came from package routing assumptions not reflected in pre-silicon model.
Compare package model versions
Audit lane mapping
Correlate SI/PI margins to failures
Ask: what baseline, owner, and artifact prove this topic is truly closed?