Package & Interface

Section goal

Bump planning, package SI/PI contracts, chip-package co-design, and package-related bring-up failure analysis.

How to study this section

1. Start with the topic hub to learn the integration contract.

2. Use mechanism and reports pages to connect contract to metrics.

3. Use debug and worked-example pages for war-room readiness.

4. Close with checklist and PPA impact before closure signoff.

Topics

1. bump-map-and-escape-planning/ — Bump Map & Escape Planning

2. package-si-pi-contracts/ — Package SI/PI Contracts

3. chip-package-io-co-design/ — Chip-Package I/O Co-design

4. package-bringup-and-failures/ — Package Bring-up & Failures

Related topics

• SoC Integration course hub

SoC deep dive

Package assumptions must be treated as first-class chip constraints.

Concept diagram

PACKAGE CO-DESIGN
die io <-> package routing <-> board constraints

Metric graph

PACKAGE RISK MIX
SI margin █████
power integrity ████
lane mapping ███

Reports and artifacts

• bump map revision log

• SI/PI margin report

• IO co-design checklist

• package bring-up failures

Mini case study

Link degradation on product board came from package routing assumptions not reflected in pre-silicon model.

Debug branches

• Compare package model versions

• Audit lane mapping

• Correlate SI/PI margins to failures

Senior review question

Ask: what baseline, owner, and artifact prove this topic is truly closed?