Part 4 answers: How do I know my RTL actually works?

The design loop is simulate, look, lint and a first synthesis check, repeated until the design and its testbench agree. This part runs that loop on mini_controller: compile and elaborate, simulate, read the waveform in GTKWave, lint with Verilator and ask Yosys what the code really infers.

Along the way it draws the line every RTL engineer must see: simulation-only code versus code that synthesizes into hardware.

After this part you can

• Run compile, simulate, view and lint on a small design and explain what each stage checks.

• Read a waveform and point to the cycle where behavior diverges from intent.

• Tell simulation-only code apart from synthesizable code and fix the mix-ups.

Lessons

Every lesson in this part is ready. Work through them in order: each one sets up the problem the next one solves.

Where other courses go deeper

This course stays on the front-end start-up path and links out instead of repeating. These lessons build on or continue what this part teaches.

• RTL: Simulation Testbenches

• RTL: Coding Lint

• Synthesis: Flow Overview

Related topics

• Course hub

• Previous: Part 3 · Specify and Architect

• Next: Part 5 · The Verification Ladder