Course map
- 1 lesson
Starts with How to Use This Course
- 1 lesson
Starts with Reading Paths
- 1 lesson
Starts with Quick Start: Your First Green Build
- 6 lessons
Starts with Idea to Silicon
- 5 lessons
Starts with Shell Survival Kit
- 3 lessons
Starts with Writing a Testable Spec
- 6 lessons
Starts with Compile, Elaborate, Simulate, Synthesize, Lint
- 6 lessons
Starts with Tests That Can Fail
- 5 lessons
Starts with Makefile for the Loop
- 3 lessons
Starts with What the Back-End Needs
- 3 lessons
Starts with Troubleshooting Table
- 3 lessons
Starts with Project: Spec to Green CI
- 4 lessons
Starts with Syntax Primer
About this course
Most courses assume you already have a working setup, know how to simulate, and can read a waveform. This course does not. It starts from no HDL, Linux or Git knowledge and carries one small design from a written specification through simulation, lint, a synthesis check and an automated build, ready to hand to the back-end team.
The path runs through nine parts: what chips are and how they get made, your workstation, writing a spec, the design loop, the verification ladder, automation, the hand-off, debugging, and a final project. Forty lessons, one running example, and links out to the deep courses wherever this course stops.
Who this is for
Complete beginners: no HDL, no Linux, no Git assumed. Start at Part 1 and read in order.
Software engineers moving into hardware: Parts 1 and 2 move fast if you already live in a shell, then the course treats RTL as a new language with new failure modes.
Students and self-learners who want one guided path instead of scattered tutorials.
What you need
A computer running macOS, Linux, or Windows through WSL, with permission to install software.
Icarus Verilog, Verilator, Yosys, Make and Git, all free and open source. Lesson 2.4 shows how to check that each one is installed and which version you have.
GTKWave for viewing waveforms is optional: the lessons show every waveform on the page.
Python 3 for the golden models. The standard library is enough.
The parts
Part | Title | The question | Lessons | Status |
|---|---|---|---|---|
1 | How does an idea become a working chip? | 6 | 6 ready | |
2 | What do I need on my machine before I can build anything? | 5 | 5 ready | |
3 | How do I write down what the design must do before I code it? | 3 | 3 ready | |
4 | How do I know my RTL actually works? | 6 | 6 ready | |
5 | How do I gain confidence the design is right, not just lucky? | 6 | 6 ready | |
6 | How do I make the whole loop rerunnable by anyone, anywhere? | 5 | 5 ready | |
7 | What does the back-end team need from me? | 3 | 3 ready | |
8 | What do I do when nothing works? | 3 | 3 ready | |
9 | Can I take a spec to green CI on my own? | 3 | 3 ready |
The running example: mini_controller
One design runs through the whole course: mini_controller, a 4-bit event counter that counts accepted events and wraps from 15 to 0. It lives in the course's example project with its spec, RTL, testbenches, golden model, Makefile, mutants and CI workflow. Part 3 specifies it, Part 4 simulates it, Part 5 tries to break it, Part 6 automates it, and Part 7 hands it off. Part 9 asks you to do the same for a second design, from a new spec.
What this course does not cover
Three reference pages round out the course: a glossary, a command cheat sheet and a tool versions page. This course stays on the front-end start-up path. Floorplan, placement, routing, sign-off timing and DRC/LVS belong to the physical-design and sign-off courses; scan, ATPG and test belong with DFT. When those topics come up, this course points at them instead of teaching them:
Constraints and the synthesis flow: Synthesis course.
Timing reports and what they mean: STA course.
Beyond the first verification ladder: full testbenches, coverage closure and UVM are in the SystemVerilog course and the UVM course.
Debugging as a discipline: Hardware Debug course.