Course map
- 1 lesson
Starts with Logic Synthesis Glossary
- 1 lesson
Starts with Logic Synthesis Cheatsheet
- 14 lessons
Starts with What Synthesis Does
- 20 lessons
Starts with Constant Propagation
- 15 lessons
Starts with Clocks and Generated Clocks
- 19 lessons
Starts with D Flop Inference
- 14 lessons
Starts with Ripple-Carry Adders
- 14 lessons
Starts with The Three-Way Trade-Off
- 15 lessons
Starts with Combinational Equivalence of RTL and Netlist
- 15 lessons
Starts with Flows as Code
- 11 lessons
Starts with Flow and Inference Questions
About this course
This course is for working RTL and verification engineers and interview candidates. It covers what a synthesis tool does to RTL, why, and how to read and steer the result, from inference to handoff.
The nine parts
Part | Topics | Lessons | Content |
|---|---|---|---|
3 | 14 | Three topics: the flow, synthesizable RTL, and reading netlists and reports. | |
4 | 20 | Four topics: Boolean optimisation, mapping, libraries, and buffering. | |
3 | 15 | Three topics: SDC constraints, delay models and slack, and timing-driven synthesis. | |
4 | 19 | Four topics: flops and resets, FSM synthesis, memory inference, and retiming. | |
3 | 14 | Three topics: adders, multipliers, and sharing arithmetic across operations. | |
3 | 14 | Three topics: trade-offs, clock gating, and scan insertion. | |
3 | 15 | Three topics: equivalence checking, ECO, and handoff to physical design. | |
3 | 15 | Three topics: scripted flows, QoR debugging, and simulation-synthesis mismatches. | |
2 | 11 | Two topics: a question bank and worked scenarios with numbers. |
How this course works
Concepts are tool-neutral: the text says a synthesis tool or the tool, never a commercial product. Constraint sketches use standard SDC names as illustrative text only.
Runnable examples use the open-source Yosys tool with ABC and a small fictional teaching library (course.lib) whose areas are library units, not a process. Timing and power use small Python models with labelled EXAMPLE parameters, and every sample report is either pinned by a runnable check or labelled illustrative.
Interview in one week
Days | Focus | Exit check |
|---|---|---|
1-2 | Sketch the flow and name what each RTL construct infers. | |
3-4 | Constrain one clock and read slack from a report. | |
5-6 | Compare adder depths and prove a netlist equals its RTL. | |
7 | Answer one bank question and one scenario with arithmetic. |
Role paths
RTL designers work the course in implementation order, ending with trade-offs and QoR. Verification engineers start from mismatch and equivalence, then add constraints and flows.
Week | RTL designer focus | Exit check |
|---|---|---|
1 | Predict the hardware for each new block before synthesis. | |
2 | Adders and Carry Structures, Resource Sharing and Arithmetic Inference | Pick the carry structure and share arithmetic deliberately. |
3 | Close a setup violation with sizing or buffering. | |
4 | Trade area, power and timing with numbers. |
Week | Verification engineer focus | Exit check |
|---|---|---|
1 | Tell a mismatch from a QoR problem. | |
2 | Prove a netlist and constrain its clocks. | |
3 | Name what retiming preserves and what scan adds. | |
4 | Rerun any result from a script and defend it. |
Keep the glossary and cheatsheet open beside any topic. The first defines terms, the second collects formulas and checklists.
Check yourself Before starting: what turns an RTL change into an accepted netlist?
Constraints that cover the design, a mapped netlist, and reports plus an equivalence proof. Synthesis Flow Overview builds the habit from the first topic.