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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
    • SDC for Synthesis
    • Delay Models and Slack
      • Arrival, Required Time and Slack
      • Setup, Hold and Clock-to-Q
      • Cell Delay Models
      • Wire Delay at Synthesis Time
      • A Static Timing Calculator
    • Timing-Driven Synthesis
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
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‹Constraints and Timing
  1. Topics
  2. Logic Synthesis
  3. Constraints and Timing
  4. Delay Models and Slack

Part 3 · Constraints and Timing · Intermediate

Delay Models and Slack

Arrival, required time, slack, and the critical path over a cell DAG.

  • 5topics
  • 5lessons

Synthesis scores every timing path with two numbers: when the signal arrives and when it is required. Their difference is the slack, and the path with the worst slack is the critical path.

Term

Meaning

Arrival time

When the signal actually reaches a point, adding clock-to-Q, cell and net delays along the path.

Required time

When the signal must reach a point, set by the clock period minus setup (or by the hold bound).

Slack

Required minus arrival. Positive means margin; negative means the path fails.

Critical path

The path with the worst (smallest) slack. It sets the maximum speed of the block.

Cell delay

Delay through a gate, from a table or linear model in the library.

Net delay

Delay along a wire, estimated at synthesis time and known only after layout.

How arrival, required time, slack and the critical path relate.
Arrival and required time give slack; the worst slack names the critical path.

Lesson

What it covers

Arrival, Required Time and Slack

Arrival, required, slack and the critical path with a worked EXAMPLE.

Setup, Hold and Clock-to-Q

Launch and capture edges, setup and hold checks, and a worked pair.

Cell Delay Models

Table versus linear cell models with a worked interpolation.

Wire Delay at Synthesis Time

Ideal-wire and wire-load estimates with a worked slack comparison.

A Static Timing Calculator

A runnable Python calculator over a small cell DAG.

Check yourself Arrival is 3.2 ns and required time is 2.9 ns. What is the slack, and does the path meet timing?

Slack is 2.9 minus 3.2, which is minus 0.3 ns. Negative slack means the path fails.

Interview

Carry one sentence per lesson: slack is required minus arrival, setup uses the next edge while hold uses the same edge, table models interpolate over slew and load, synthesis wires are estimates, and a calculator propagates arrival forward and required backward.

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See also

  • SDC for Synthesis
  • Timing-Driven Synthesis