Elaboration

Building a generic hardware structure of operators, muxes and registers from RTL, before optimisation.

Synthesis Flow Overview

Generic netlist

The tool-independent netlist of generic operators produced by elaboration, before technology mapping.

Synthesis Flow Overview

Mapped netlist

A netlist of standard cells from the target library, produced by technology mapping.

Technology Mapping

Technology mapping

Covering a Boolean network with standard cells so cost is minimised under delay constraints.

Technology Mapping

Boolean optimisation

Two-level and multi-level logic minimisation before mapping, using factoring and don't-care sets.

Boolean Optimization

Don't-care

Input combinations or outputs the function never uses, which optimisation may assign freely.

Boolean Optimization

Restructuring

Rebalancing logic trees, such as a chain into a tree, to cut depth at some area cost.

Structuring and Buffering

Buffering

Inserting buffers or inverter pairs to isolate loads and repair slew and capacitance violations.

Structuring and Buffering

Sizing

Swapping cell drive strengths to trade delay against area and power on chosen paths.

Timing-Driven Synthesis

dont_touch

An attribute marking a net or cell the tool must preserve, blocking optimisation across it.

Timing-Driven Synthesis

Timing-driven synthesis

Optimisation guided by slack: sizing, buffering and restructuring aimed at violating paths.

Timing-Driven Synthesis

Resource sharing

Implementing mutually exclusive operations on one unit, such as one adder for two branches.

Resource Sharing and Arithmetic Inference

Standard cell

A fixed-height, variable-width library gate with characterised timing, power and area.

Cell Libraries and Liberty

Liberty library

The library format carrying NLDM tables, cell areas, leakage and pin data for mapping.

Cell Libraries and Liberty

NLDM table

Non-linear delay model: lookup tables of cell delay and output slew indexed by input slew and load.

Cell Libraries and Liberty

Drive strength

A cell variant's output current capability; stronger variants drive larger loads faster at more area.

Cell Libraries and Liberty

Fanout

The number of driven inputs on a net; large fanout slows the driver and may need buffering.

Structuring and Buffering

Slew

Transition time of a signal edge between fixed thresholds; slow slews delay the driven cells.

Delay Models and Slack

Arrival time

The latest (setup) or earliest (hold) time a signal reaches a point, from launch plus path delay.

Delay Models and Slack

Required time

The latest (setup) or earliest (hold) time a signal may reach a point and still meet the check.

Delay Models and Slack

Slack

Required time minus arrival time on a setup path; hold slack is the earliest arrival minus the hold required time. Non-negative slack meets timing.

Delay Models and Slack

WNS

Worst (minimum) slack over all checked paths; negative when timing fails.

Delay Models and Slack

TNS

Total negative slack: the sum of all negative endpoint slacks; zero means no violating endpoint.

Delay Models and Slack

Critical path

The longest checked setup path under the active constraints, which sets the maximum clock frequency.

Delay Models and Slack

Setup time

How long data must be stable before the clock edge at a flop input.

Delay Models and Slack

Hold time

How long data must stay stable after the clock edge at a flop input.

Delay Models and Slack

SDC

SDC: the widely used text format for clocks, IO delays and timing exceptions.

SDC for Synthesis

Clock uncertainty

Margin covering jitter and pre-layout skew, subtracted from the available time.

SDC for Synthesis

Input delay

SDC bound on latest and earliest arrival at an input port, standing in for the driver.

SDC for Synthesis

Output delay

SDC bound on external setup and hold at an output port, standing in for the receiver.

SDC for Synthesis

False path

A path exempt from checks because it is never exercised functionally.

SDC for Synthesis

Multicycle path

A path allowed more than one clock cycle, checked at the stated cycle multiplier.

SDC for Synthesis

Inference

The hardware a synthesis tool builds from an RTL construct.

Synthesizable RTL and Inference

Latch inference

Unintentional level-sensitive storage built when combinational code leaves an output unassigned.

Synthesizable RTL and Inference

Reset

Synchronous reset acts through the data path and needs a clock; asynchronous reset is immediate and needs synchronised release.

Flops, Resets and Enables

Clock enable

A flop enable that holds state without gating the clock.

Flops, Resets and Enables

One-hot encoding

State encoding with one flop per state and exactly one active; fast decode at the cost of one flop per state.

FSM Synthesis

FSM encoding

State assignment choice: binary is compact, Gray coding assigns codes that differ by one bit to states adjacent in sequence, reducing transitions for sequential traversals, while arbitrary jumps can still change several bits, and one-hot is fastest to decode at the cost of one flop per state.

FSM Synthesis

Memory inference

The tool mapping an array with read and write patterns to a memory macro instead of flops.

Memory and Macro Inference

Retiming

Moving registers across combinational logic to balance stage delays without changing cycle behaviour.

Retiming and Pipelining

Ripple-carry adder

N-bit ripple adder with a half-adder LSB and no carry-in: N minus 1 full-adder carry stages on the carry path; with a carry-in the LSB is a full adder and there are N.

Adders and Carry Structures

Carry-lookahead

Group generate and propagate signals computed in parallel to break the linear carry chain.

Adders and Carry Structures

Prefix adder

A parallel-prefix carry network, such as Kogge-Stone, Sklansky or Brent-Kung, with O(log N) depth.

Adders and Carry Structures

Booth recoding

Recoding multiplier bits in overlapping groups so each partial product is 0 or a small multiple of the multiplicand.

Multipliers and Compressors

Compressor

A circuit reducing several same-weight bits to fewer bits, such as four inputs to sum plus carry.

Multipliers and Compressors

Carry-save adder

An adder keeping sum and carry separate with no carry propagation, compressing three rows to two.

Multipliers and Compressors

Wallace tree

A tree of carry-save adders compressing many partial products to two rows, finished by one adder.

Multipliers and Compressors

Dynamic power

Charging power alpha times C times V squared times f, spent only when nets toggle.

Area, Power and Timing Tradeoffs

Leakage power

Static power from subthreshold and gate leakage, drawn with power on and no toggling.

Area, Power and Timing Tradeoffs

Switching activity

The average number of transitions per clock cycle for a net, in toggles per cycle.

Area, Power and Timing Tradeoffs

Clock gating

Disabling clock toggles to idle registers to save dynamic power.

Clock Gating and Low Power

ICG

Integrated clock-gating cell: a latch plus AND gate packaged so that a correctly timed enable does not glitch the clock.

Clock Gating and Low Power

Scan

Test structures threading flops into shift chains so patterns can control and observe internal state.

DFT and Scan Insertion

Equivalence checking

Formal proof that a netlist behaves like its RTL on all sequences from reset.

Equivalence Checking

Miter

A circuit XORing pairwise outputs of two designs and ORing the results; constant zero proves equivalence.

Equivalence Checking

ECO

Engineering change order: a small late fix applied to the mapped netlist with minimal disturbance.

Incremental Compile and ECO

Incremental compile

Re-running synthesis on part of a design while preserving the rest, for fast ECO turnaround.

Incremental Compile and ECO

Wire-load model

A statistical capacitance estimate from fanout used before placement; later replaced by extraction.

Physical-Aware Synthesis and Handoff

Congestion

Routing demand exceeding track supply in a region; spread or duplicated logic can worsen it.

Physical-Aware Synthesis and Handoff

Handoff

The package for physical design: mapped netlist, constraints, assumptions and labelled reports.

Physical-Aware Synthesis and Handoff

QoR

Quality of results: the measured area, timing and power of a synthesis run.

Debugging QoR

Scripted flow

A checked-in sequence of synthesis steps plus regression checks reproducing every QoR number.

Scripted Flows and Regression

Simulation-synthesis mismatch

Behaviour differing between RTL simulation and the netlist, from X handling, latches or async logic.

Simulation-Synthesis Mismatch

X-optimism

Simulation resolves an unknown favourably while synthesis is free to implement either value, so silicon can disagree with simulation.

Simulation-Synthesis Mismatch