Technology mapping covers an optimised Boolean network with cells from the library. Each gate becomes part of exactly one cell, and the choice trades area against delay.
Lesson | What it covers |
|---|---|
Subject graphs, patterns, covers, and a first area comparison. | |
k-feasible cuts and a runnable tree-covering toy. | |
Area cost, arrival times, slack, and the cheapest cell losing. | |
Bubble pushing, polarity choice, and dont_use cells. | |
A 4-bit adder mapped with ABC to two library variants. |
When delay matters more than area on that path, or when the cell cannot drive its load within the slew limit.