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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
    • Scripted Flows and Regression
    • Debugging QoR
    • Simulation-Synthesis Mismatch
  • Interview and Judgment11
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‹Logic Synthesis
  1. Topics
  2. Logic Synthesis
  3. Flows and Debugging

Part 8 · Flows and Debugging · Intermediate

Flows and Debugging

Scripted flows, QoR debugging, and simulation-synthesis mismatches.

  • 3topics
  • 15lessons

This part makes results repeatable after handoff rules are set. Scripted flows and regression pin versions and thresholds, and QoR debugging reproduces, isolates, and classifies poor results. Mismatch rules keep simulation and the synthesised netlist in agreement.

Learning path through the flows and debugging topics.
Suggested order. Flows first, then debugging, then mismatches.

The three topics

Topic

Lessons

Description

Time

Scripted Flows and Regression

5

Flows as code, QoR extraction, and nightly regression with thresholds.

40 min

Debugging QoR

5

A method for poor QoR: reproduce, isolate the worst path, classify, fix.

40 min

Simulation-Synthesis Mismatch

5

Sensitivity lists, blocking versus non-blocking, X handling, case priority, and gate simulation.

40 min

Tip

Pin versions and thresholds before reading a trend: library, tool, and script versions plus a noise band turn wiggles into signals.

Check yourself A QoR number moves after an RTL change. What is the first question?

Is the run reproducible: same versions, same constraints, same script. The Scripted Flows and Regression topic sets that bar before any debug.

Interview

Typical screening questions from this part: noise versus regression, the QoR debug method, and one simulation-synthesis mismatch with its rule.

Related topics

  • Up: Logic Synthesis course hub

  • Previous: Verification, ECO and Handoff

  • Next: Interview and Judgment

  • See also: Synthesis Foundations

  • See also: Logic Optimisation and Mapping

  • See also: Constraints and Timing

  • See also: Sequential, FSM and Memory

  • See also: Datapath Synthesis

  • See also: Area, Power and Test

PreviousNext: Scripted Flows and Regression

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See also

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations