Simulation-Synthesis Mismatch · synthesis

Part 8 · Flows and Debugging · Intermediate

Simulation and synthesis can disagree on the same RTL. This topic collects the classic disagreements and the coding rule that prevents each one.

Mismatch	Simulation shows	The gates build	Preventing rule
Incomplete sensitivity list	A stale value until a listed signal moves	The combinational body	Complete the list or use `always_comb`
Blocking versus non-blocking	Order-dependent updates in one step	Parallel registers or plain gates	`=` in combinational code, `<=` in clocked code
X in a condition or select	The else path or the default branch	One concrete path for a real 0 or 1	Reset before use and never decide on `x`
Overlapping case items	First match wins	First match wins, unless a parallel promise said otherwise	Write the priority plainly or prove one-hot
Build-hidden code and widths	Test helpers and wide constants	Trimmed logic with no test region	Keep non-build code out and size every constant

Two views of one RTL intent compared by gate simulation.

RTL simulation and the gate netlist are two views of one intent; gate simulation compares them.

Lesson	What it covers
Sensitivity lists and races	Stale outputs, ignored event lists, and races between concurrent blocks.
Blocking and non-blocking	Immediate versus clocked updates with a worked shift trace.
X pessimism, optimism, and init	Four-state surprises and the reset rule.
Case priority and wildcards	Overlapping items, `casez` and `casex`, with a demo and a proof.
Directives, widths, and gate simulation	Hidden regions, truncation, and zero-delay versus timed simulation.

Check yourself A testbench passes but the gate netlist misbehaves on one vector. Where do you look first?

The mismatch list: sensitivity, blocking assignments, X handling, and case priority. Reproduce the vector at the gate level before blaming the tool.

Mismatch

Simulation shows

The gates build

Preventing rule

Incomplete sensitivity list

A stale value until a listed signal moves

The combinational body

Complete the list or use always_comb

Blocking versus non-blocking

Order-dependent updates in one step

Parallel registers or plain gates

= in combinational code, <= in clocked code

X in a condition or select

The else path or the default branch

One concrete path for a real 0 or 1

Reset before use and never decide on x

Overlapping case items

First match wins

First match wins, unless a parallel promise said otherwise

Write the priority plainly or prove one-hot

Build-hidden code and widths

Test helpers and wide constants

Trimmed logic with no test region

Keep non-build code out and size every constant

Lesson

What it covers

Stale outputs, ignored event lists, and races between concurrent blocks.

Immediate versus clocked updates with a worked shift trace.

Four-state surprises and the reset rule.

Overlapping items, casez and casex, with a demo and a proof.

Hidden regions, truncation, and zero-delay versus timed simulation.