Logic Synthesis Cheatsheet

Logic Synthesis · Intermediate

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One page for the flow, the formulas and the checklists. Every number below uses labelled EXAMPLE parameters in a fictional teaching setup.

Synthesis flow

Stage	What it does
Elaborate	Builds a generic netlist of operators, muxes and registers from RTL.
Generic optimise	Simplifies, narrows, shares and re-encodes before any library exists.
Map	Covers logic with course.lib cells and library flops.
Timing-driven optimise	Sizes, buffers and restructures critical paths against constraints.
Report	Area, timing and power numbers for the mapped netlist.
Verify and hand off	Equivalence proof plus netlist, constraints and labelled reports for layout.

RTL to hardware

RTL construct	Inferred hardware
`a & b`, `a \| b`, `a ^ b`	AND, OR and XOR gates.
`?:` and if-else	A 2:1 mux; nested conditions form a priority chain.
case	A wide mux or decoder.
`+` and `-`	An adder or subtractor; the carry structure is chosen at mapping.
`*`	A multiplier: Booth recoding plus a compressor tree.
`==` and `<`	A comparator, built like a subtract without the sum.
`<<` and `>>`	A shifter; a constant shift is wiring.
Incomplete combinational assignment	A latch holding the unassigned case.
Posedge block with reset	A DFF with synchronous or asynchronous reset.
Array with read and write patterns	A memory macro, else flops.

Timing equations

Symbol	Meaning	Units
`T_clk`	Clock period	ns
`t_cq`	Clock-to-Q of the launch flop	ns
`t_comb`	Combinational delay to the capture D input	ns
`t_setup`, `t_hold`	Setup and hold of the capture flop	ns
`t_uncert`	Clock uncertainty from jitter and skew margin, with separate setup and hold values	ns
`D_in`, `D_out`	SDC input and output delays	ns

s l a c k_{se t u p} = r e q u i r e d - a r r i v a l

A setup path meets timing when slack is non-negative. Arrival is launch latency plus t_cq plus t_comb; required is one period plus capture latency minus launch latency, minus t_setup and t_uncert.

With balanced clocks the setup required time is T_clk - t_setup - t_uncert. The hold check mirrors it: hold slack is minimum arrival minus the hold required time t_hold + t_uncert.

Input paths budget the driver: setup available is T_clk - t_setup - t_uncert - D_in,max. Output paths budget the receiver: setup available is T_clk - D_out,max - t_uncert.

Illustrative SDC sketch. Command names are standard; values are invented and the block does not run.

Diagram

# illustrative - invented values, not run
create_clock -period 10.0 [get_ports clk]
set_input_delay -max 4.0 -clock clk [all_inputs]
set_output_delay -max 3.0 -clock clk [all_outputs]
set_false_path -from [get_ports rst_n]
set_multicycle_path 2 -setup -from [get_cells slow_a] -to [get_cells slow_b]

Diagram

EXAMPLE parameters: T_clk = 10.0 ns, t_cq = 0.5 ns, t_comb = 6.0 ns
t_setup = 0.4 ns, t_uncert,setup = 0.3 ns
arrival  = 0.5 + 6.0 = 6.5 ns
required = 10.0 - 0.4 - 0.3 = 9.3 ns
setup slack = 9.3 - 6.5 = 2.8 ns (meets timing)
hold: t_cq,min = 0.3 ns, t_comb,min = 0.8 ns, t_hold = 0.2 ns, t_uncert,hold = 0.1 ns
hold slack = (0.3 + 0.8) - (0.2 + 0.1) = 1.1 - 0.3 = 0.8 ns (meets timing)
input path: D_in,max = 4.0 ns -> available = 10.0 - 0.4 - 0.3 - 4.0 = 5.3 ns
output path: D_out,max = 3.0 ns -> available = 10.0 - 3.0 - 0.3 = 6.7 ns

Power

Symbol	Meaning	Units
`alpha`	Switching activity, toggles per clock cycle	unitless
`C`	Switched capacitance	F
`V`	Supply voltage	V
`f`	Clock frequency	Hz
`P`	Power	W

P_{d y n} = a l p ha \cdot C \cdot V^{2} \cdot f

Dynamic power charges and discharges switched capacitance, so only toggling nets spend it. Leakage from subthreshold and gate currents flows with power on and no toggling.

Clock gating cuts dynamic power by stopping idle toggles. Leakage needs fewer or less leaky cells, or power gating.

Diagram

EXAMPLE parameters: alpha = 0.2 toggles/cycle, C = 50 pF, V = 0.8 V, f = 500 MHz
P_dyn = 0.2 x 50e-12 F x (0.8 V)^2 x 500e6 Hz
      = 0.2 x 50e-12 x 0.64 x 500e6 W
      = 0.2 x 0.016 W = 0.0032 W = 3.2 mW
leakage note: P_leak = V x I_leak = 0.8 V x 2.0 mA = 1.6 mW (EXAMPLE I_leak)

Prefix adders

Depth counts prefix-operator levels on the longest path. Operator counts exclude input buffers and final sum XORs; every prefix row assumes N is a power of two. Ripple rows use the half-adder LSB convention: with no carry-in the LSB is a half adder and the carry path has N minus 1 full-adder stages; with a carry-in the LSB is a full adder and there are N.

Architecture	Depth	Prefix operators
Ripple-carry	N - 1 carry stages, half-adder LSB (N with a carry-in)	N - 1 full adders plus the half-adder LSB (N full adders with a carry-in)
Kogge-Stone	log2 N	N x log2 N - N + 1
Sklansky	log2 N	(N / 2) x log2 N
Brent-Kung	2 x log2 N - 1	2N - 2 - log2 N

Diagram

N = 8, L = log2 8 = 3
Kogge-Stone: depth 3; operators 8x3 - 8 + 1 = 24 - 8 + 1 = 17
Sklansky: depth 3; operators (8/2)x3 = 4x3 = 12
Brent-Kung: depth 2x3 - 1 = 5; operators 2x8 - 2 - 3 = 16 - 2 - 3 = 11
ripple (half-adder LSB): depth 8 - 1 = 7 carry stages; 7 full adders plus the half-adder LSB
N = 16, L = 4: KS depth 4 and 49 operators; Sklansky depth 4 and 32
Brent-Kung depth 7 and 26; ripple 15 carry stages (15 full adders plus the half-adder LSB)

example.py

import sys

def log2int(n):
    l = 0
    while (1 << l) < n:
        l += 1
    if (1 << l) != n:
        print("FAIL: N=" + str(n) + " is not a power of two")
        sys.exit(1)
    return l

def ks_model(n):
    l = log2int(n)
    nodes = 0
    for k in range(l):
        nodes += n - (1 << k)
    return l, nodes

def sk_model(n):
    l = log2int(n)
    def rec(m):
        if m == 2:
            return 1
        return 2 * rec(m // 2) + m // 2
    return l, rec(n)

def bk_model(n):
    l = log2int(n)
    fwd = 0
    full = set()
    for k in range(l):
        step = 1 << (k + 1)
        i = step - 1
        while i < n:
            fwd += 1
            if i - step + 1 == 0:
                full.add(i)
            i += step
    inv = (n - 1) - len(full)
    return 2 * l - 1, fwd + inv

def ripple_model(n):
    stages = 0
    for _ in range(1, n):
        stages += 1
    full_adders = 0
    for _ in range(1, n):
        full_adders += 1
    return stages, full_adders

def check(n, got, want):
    if got != want:
        print("FAIL: N=" + str(n) + " got " + str(got) + " want " + str(want))
        sys.exit(1)

for n in (8, 16):
    l = log2int(n)
    check(n, ks_model(n), (l, n * l - n + 1))
    check(n, sk_model(n), (l, (n // 2) * l))
    check(n, bk_model(n), (2 * l - 1, 2 * n - 2 - l))
    check(n, ripple_model(n), (n - 1, n - 1))

print("PASS: prefix depths and node counts match closed forms for N=8 and N=16")

Yosys passes

Only these passes appear in course examples, with inline Verilog and assertions on each claim. Flags beyond the kit conventions are left out.

Pass	What it does
read_verilog	Parses inline Verilog into the RTLIL database.
hierarchy	Resolves module hierarchy and elaborates parameters.
proc	Turns always-block processes into muxes and flops.
opt	Runs the bundled generic simplifications: constants, merging and dead logic.
wreduce	Narrows operators whose upper bits are unused.
alumacc	Groups add, subtract and multiply operators into word-level cells.
share	Shares one operator across mutually exclusive branches.
memory	Collects arrays into memory cells for macro inference.
fsm	Detects state machines and re-encodes their states.
techmap	Maps generic cells to gate-level cells.
abc	Optimises and maps combinational logic, optionally to course.lib cells.
dfflibmap	Maps internal flops to course.lib DFF cells.
stat	Reports cell counts and library-unit area.
sat	Proves a property over the design, such as a miter output always reading zero.
miter	Builds a circuit that flags any output mismatch between two designs.
equiv_make, equiv_simple and equiv_status	Set up, simplify and report an equivalence check built around a miter.
select	Selects design objects and asserts expected counts.

Debugging poor QoR

Check	Action
Constraints complete	Every clock is created and every IO delayed; unconstrained paths report best-effort numbers.
Generic against mapped	Compare pre-mapping area with mapped area to separate an RTL cause from a mapping cause.
Worst path cells	Read the top violating path: an operator chain, a deep mux, or a long wire-load guess.
Arithmetic shape	Wide adders, comparators and priority chains dominate delay; revisit the datapath choice.
Fanout and slew	High-fanout nets and slow slews point at missing buffering.
Blocked optimisation	dont_touch and preserved hierarchy stop cross-boundary optimisation; lift them deliberately.
Over-constraining	Missing false and multicycle declarations overwork logic that never needs speed.
Library choice	Weak drives on critical outputs and hot leaky cells; resize only the critical ones.
Mismatch before QoR	Wrong behaviour is a mismatch (X handling, latches, async logic), not a QoR problem; prove equivalence first.

Interview-answer skeleton

Step	Say	Ground it
Name the hardware	One sentence: what the RTL infers.	A cell or operator count.
State the constraint	The clock, IO delays and exceptions covering the path.	Numbers with units.
Read the report	Slack, area and the worst cell.	One quoted line.
Name the lever	Resize, buffer, restructure, share or retime.	Expected effect and its cost.
Prove it	Re-run, equivalence and regression.	A PASS line or a clean report.

Navigate

Synthesis flow

RTL to hardware

Timing equations

Power

Prefix adders

Yosys passes

Debugging poor QoR

Interview-answer skeleton

Related topics

Logic Synthesis Cheatsheet

Synthesis flow

RTL to hardware

Timing equations

Power

Prefix adders

Yosys passes

Debugging poor QoR

Interview-answer skeleton

Related topics

Synthesis flow

RTL to hardware

Timing equations

Power

Prefix adders

Yosys passes

Debugging poor QoR

Interview-answer skeleton

Related topics

Up next

Synthesis flow

RTL to hardware

Timing equations

Power

Prefix adders

Yosys passes

Debugging poor QoR

Interview-answer skeleton

Related topics

Up next