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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
    • Adders and Carry Structures
    • Multipliers and Compressors
    • Resource Sharing and Arithmetic Inference
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
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‹Logic Synthesis
  1. Topics
  2. Logic Synthesis
  3. Datapath Synthesis

Part 5 · Datapath Synthesis · Intermediate

Datapath Synthesis

Adders, multipliers, and sharing arithmetic across operations.

  • 3topics
  • 14lessons

This part covers arithmetic once sequential elements are in place. Adder families trade depth against area, and multiplier stages run from recoding through compressor trees to the final add. Sharing then reuses operators across operations only where the mux cost wins.

Learning path through the datapath topics.
Suggested order. Adders first, then multipliers, then sharing.

The three topics

Topic

Lessons

Description

Time

Adders and Carry Structures

5

Ripple, lookahead, select, and prefix adders as depth-area trade-offs.

40 min

Multipliers and Compressors

5

Booth recoding, compressor trees, and the final adder.

40 min

Resource Sharing and Arithmetic Inference

4

Sharing adders across operations, and when the mux costs more.

32 min

Tip

Verify every arithmetic model against plain integer math on small widths before trusting its counts. Exhaustive small-width checks catch formula slips.

Check yourself Why check a prefix-adder depth formula against integers instead of trusting the algebra?

Off-by-one slips in depth and node counts are invisible in symbols but fail on 4-bit and 8-bit cases. The Adders and Carry Structures topic builds those checks.

Interview

Typical screening questions from this part: prefix-adder depth for N bits, Booth recoding benefit, and the break-even rule for sharing an adder.

Related topics

  • Up: Logic Synthesis course hub

  • Previous: Sequential, FSM and Memory

  • Next: Area, Power and Test

  • See also: Synthesis Foundations

  • See also: Logic Optimisation and Mapping

  • See also: Constraints and Timing

  • See also: Verification, ECO and Handoff

  • See also: Flows and Debugging

  • See also: Interview and Judgment

PreviousNext: Adders and Carry Structures

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Up nextAdders and Carry Structures

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See also

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations