This part covers state after combinational mapping is understood. Flop, reset, and enable idioms decide which library cells are inferred, and FSM style and encoding shape the result. Arrays split into flops or RAM macros, and retiming balances stages while preserving the steady-state output stream.
Topic | Lessons | Description | Time |
|---|---|---|---|
5 | D flops, enables, resets, and how each maps to library cells. | 40 min | |
5 | Coding styles, state encoding, and safe recovery from unreachable states. | 40 min | |
4 | When arrays become flops and when they become RAM macros. | 32 min | |
5 | Moving registers across logic to balance stages while keeping the steady-state output stream. | 40 min |
Retiming moves registers but not reset intent, so a balanced pipeline can still reset wrong. The Retiming and Pipelining topic lists the reset checks.