Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
    • SDC for Synthesis
    • Delay Models and Slack
    • Timing-Driven Synthesis
      • Critical-Path Focus
      • Restructuring and Duplication
      • Sizing and Path Groups
      • Reading WNS and TNS
      • Margin and When to Stop
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
Loading lesson

‹Timing-Driven Synthesis
  1. Topics
  2. Logic Synthesis
  3. Constraints and Timing
  4. Timing-Driven Synthesis
  5. Margin and When to Stop

Part 3 · Constraints and Timing · Intermediate

Margin and When to Stop

Over-constraining margin: how much helps, when it harms, and when to stop.

On this page

    A little margin guards the handoff

    Synthesis models differ slightly from later stages, so closing exactly at zero can reopen downstream. A small margin holds slack back for that gap.

    Margin means constraining synthesis to a target tighter than the real one. The calc block works a 1.0-unit margin on a 10.0-unit period.

    Diagram
    EXAMPLE parameters: clock period 10.0 time units, margin 1.0 time units
    synthesis target = 10.0 - 1.0 = 9.0 time units
    tool closes with arrival 8.8: tool slack = 9.0 - 8.8 = +0.2
    handoff slack at the real period = 10.0 - 8.8 = +1.2

    Too much margin distorts the design

    A large margin spends area and power on a fiction. The tool reshapes logic for a target the design never needs to meet.

    Those shapes can hurt the true paths: deeper area, larger loads, and structures that later stages must undo. Margin beyond the real uncertainty buys risk, not safety.

    Rules for stopping

    Effort stops when the numbers and the budget agree. Each rule below is a separate reason to quit a failing path or a finished job.

    • WNS reaches zero at the synthesis target including margin: the job is done.

    • TNS stays flat across two runs while area still grows: restructure instead of sizing further.

    • Each run moves the worst path somewhere new with no global gain: the structure is spent, so change it or accept the result.

    • Area or power hits its budget: further timing effort spends what the design cannot afford.

    Common mistakes

    Common pitfall

    Raising the margin to force a stubborn path usually backfires. The tool overworks easy paths and distorts the netlist while the true limiter stays untouched.

    Interview

    Likely probes: margin sizing and stop signals.

    • Margin covers model gaps to the next stage; 1.0 on 10.0 here leaves 1.2 at handoff.

    • Excess margin spends area on a fiction and can harm true paths.

    • Flat TNS with growing area means restructure or stop, not more sizing.

    Check yourself The tool closes at 8.8 arrival against a 9.0 synthesis target with a 10.0 period. What is the handoff slack?

    +1.2 time units. Handoff slack is 10.0 minus 8.8.

    Check yourself TNS is flat across two runs while area keeps growing. What is the right move?

    Stop sizing and restructure, or stop entirely. More of the same effort spends area without gain.

    Related topics

    • Up: Timing-Driven Synthesis

    • Critical-Path Focus

    • Area, Power and Timing Tradeoffs

    Previous

    51 / 139

    Next: Sequential, FSM and Memory

    Up next

    Up nextSequential, FSM and Memory

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Critical-Path Focus
    • Restructuring and Duplication
    • Sizing and Path Groups