Synthesis optimises against the constraints it is given: clocks set the target, input and output delays bound the IO paths, and exceptions mark the paths that play by different rules. A missing constraint is an unconstrained path, not a free pass.
Constraint | What it tells the tool |
|---|---|
create_clock | The clock name and its EXAMPLE period, which sets the timing target. |
Uncertainty and latency | Margin for skew and jitter, and the delay from the source to the flop clock pin. |
set_input_delay, set_output_delay | How much of the period the outside world already consumes on each IO path. |
set_driving_cell, set_load | The drive behind each input and the capacitance on each output. |
Exceptions | False paths, multicycle paths, case analysis and maximum-delay bounds. |
Lesson | What it covers |
|---|---|
Periods, generated clocks at concept level, and units. | |
Uncertainty, latency, input and output delays, and available time. | |
Drive models, load models, and EXAMPLE units. | |
Exceptions: false paths, multicycle, case analysis, maximum delay. | |
Unconstrained paths, over-constraining, and a tiny checker. |
The tool cannot time it, so it is optimised without a target. Unconstrained paths are a closure risk, not a timing win.