A clock constraint names a clock and states its EXAMPLE period in nanoseconds. The period is the budget every path on that clock is measured against.
Without a clock constraint the tool has no target for the paths on that clock. Those paths are unconstrained, and the lesson on missing constraints shows why that is a risk.
A generated clock is derived from a master clock inside the design, for example by dividing it. The concept is a source clock plus a relationship, such as divide-by-2.
Generated-clock handling varies between tools, so state the source and the relationship explicitly. The listing below sketches the idea in tool-neutral form.
The listing below is illustrative tool-neutral SDC and is not run by any tool.
illustrative SDC sketch (not run by any tool):
create_clock -name CLK -period 10.0 [get_ports clk]
# generated-clock sketch: source plus relationship; exact option spelling varies between tools
create_generated_clock -name DIV2 -source CLK -divide_by 2 [get_pins div_q]Frequency is one divided by the period. Both numbers below are EXAMPLE parameters with stated units.
EXAMPLE parameters (not real targets): master period 10.0 ns
frequency = 1 / period = 1 / (10.0 x 10^-9 s) = 100 x 10^6 Hz = 100 MHz
divide-by-2 clock: period = 2 x 10.0 ns = 20.0 ns
generated frequency = 1 / (20.0 x 10^-9 s) = 50 MHzCommand idea | Purpose |
|---|---|
create_clock | Names the clock and states its EXAMPLE period. |
Generated-clock sketch | Names the derived clock, its source, and the divide or multiply relationship. |
100 MHz. Frequency is 1 divided by 10.0 ns, which is 100 x 10^6 Hz.
Period 20.0 ns and frequency 50 MHz. Doubling the period halves the frequency.