Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
    • SDC for Synthesis
      • Clocks and Generated Clocks
      • Uncertainty, Latency and IO Delays
      • Driving Cells, Loads and Units
      • False, Multicycle and Max-Delay Paths
      • Missing and Over-Tight Constraints
    • Delay Models and Slack
    • Timing-Driven Synthesis
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
Loading lesson

‹SDC for Synthesis
  1. Topics
  2. Logic Synthesis
  3. Constraints and Timing
  4. SDC for Synthesis
  5. False, Multicycle and Max-Delay Paths

Part 3 · Constraints and Timing · Intermediate

False, Multicycle and Max-Delay Paths

Exceptions that change the rules: false paths, multicycle, case analysis, max delay.

On this page

    False paths

    A false-path exception marks paths that cannot switch in the real design, such as crossings between unrelated test and mission logic. The tool stops optimising them against the clock.

    A false path must be truly impossible, not merely slow. Marking a real path false hides its failure instead of fixing it.

    Multicycle paths

    A multicycle exception gives a path more than one clock period, for logic that is validly sampled late, such as an enable-gated datapath. The setup check moves out to the stated number of cycles (a multicycle value of 2 allows two cycles from launch to capture).

    How the tool pairs the setup and hold checks for multicycle paths varies, so state both parts explicitly. The listing below sketches the setup part in tool-neutral form.

    The listing below is illustrative tool-neutral SDC and is not run by any tool.

    Diagram
    illustrative SDC sketch (not run by any tool):
    set_false_path -from [get_ports test_en] -to [get_clocks CLK]
    set_multicycle_path -setup 2 -from [get_cells slow_a] -to [get_cells slow_b]
    # hold pairing for multicycle paths varies between tools; state it explicitly

    Case analysis and maximum delay

    Case analysis pins a pin or port to a constant value, so the tool analyses only the paths that are live under that value. It models a mode tie without changing the RTL.

    A maximum-delay exception bounds named paths directly in EXAMPLE nanoseconds, independent of the clock period. It suits paths whose budget is not one period, such as a short handshake.

    The listing below is illustrative tool-neutral SDC and is not run by any tool.

    Diagram
    illustrative SDC sketch (not run by any tool):
    set_case_analysis 0 [get_ports test_en]
    set_max_delay 4.0 -from [get_cells slow_a] -to [get_cells slow_b]

    Exception

    Effect

    Risk if wrong

    False path

    Path is not timed against the clock

    A real path escapes timing entirely.

    Multicycle path

    Setup check moves out to the stated number of cycles

    A one-cycle path is given time it does not have.

    Case analysis

    Only the tied value is analysed

    Paths live under the other value are ignored.

    Maximum delay

    Path is bounded in EXAMPLE ns

    A budget detached from the clock drifts when the period changes.

    Common pitfall

    Exceptions are claims about the design, and the tool trusts them silently. Re-check every exception against the RTL after each change: a renamed enable or a retimed handshake turns a true exception into a hidden failure.

    Interview

    Likely probes: when each exception fits, and what breaks when it is wrong.

    • False paths fit paths that cannot switch; multicycle fits paths sampled late by design.

    • Case analysis fits mode ties; maximum delay fits budgets that are not one period.

    • Every wrong exception hides a failure instead of fixing one.

    Check yourself A path is marked false but can switch in mission mode. What is the result?

    The tool stops timing it, so its failure is hidden. A false path must be truly impossible.

    Check yourself A multicycle setup of 2 is set without stating the hold part. What is missing?

    The hold pairing, which varies between tools. State both parts explicitly.

    Related topics

    • Missing and Over-Tight Constraints

    • Timing-Driven Synthesis

    • See also: Timing Exceptions

    Previous

    40 / 139

    Next: Missing and Over-Tight Constraints

    Up next

    Up nextMissing and Over-Tight Constraints

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Clocks and Generated Clocks
    • Uncertainty, Latency and IO Delays