A path with no clock or IO constraint covering it is unconstrained. The tool optimises it without a target, which is a closure risk rather than a timing win.
Common causes are a missing clock, missing input or output delays, and exceptions that silently remove paths. Coverage of constraints matters as much as their values.
Over-constraining states a target tighter than the real requirement, such as a shorter EXAMPLE period. The tool spends area and power chasing a fiction.
The spend can also hurt the true paths by pushing the tool into structures that serve the false target. Margin belongs where variation is real, and it is revisited in timing-driven synthesis.
The program below parses a small SDC subset: create_clock lines and set_input_delay lines. It reports which input ports of a port list have no input delay.
Its three self-checks pin the parsed clock, the constrained ports, and the missing ports. The port list and the SDC lines are fixed parameters of the program.
import sys
SDC = [
"create_clock -name CLK -period 10.0 [get_ports clk]",
"set_input_delay -clock CLK 3.0 [get_ports req]",
"set_input_delay -clock CLK 3.0 [get_ports data]",
]
PORTS = ["req", "data", "ack", "valid"]
def ports_in(line):
start = line.find("[get_ports ")
if start < 0:
return []
inner = line[start + len("[get_ports "):]
end = inner.find("]")
if end < 0:
return []
return inner[:end].split()
clocks = {}
constrained = set()
for line in SDC:
text = line.strip()
if text.startswith("create_clock"):
parts = text.split()
name = parts[parts.index("-name") + 1]
period = float(parts[parts.index("-period") + 1])
clocks[name] = period
if text.startswith("set_input_delay"):
for p in ports_in(text):
constrained.add(p)
missing = [p for p in PORTS if p not in constrained]
if clocks != {"CLK": 10.0}:
print("FAIL: clocks parsed as " + str(clocks))
sys.exit(1)
if sorted(constrained) != ["data", "req"]:
print("FAIL: constrained parsed as " + str(sorted(constrained)))
sys.exit(1)
if missing != ["ack", "valid"]:
print("FAIL: missing parsed as " + str(missing))
sys.exit(1)
print("PASS: 2 of 4 input ports lack an input delay: ack and valid")Symptom | Cause | Fix |
|---|---|---|
Unconstrained paths | Missing clock, IO delay, or an over-wide exception | Add the missing bound; narrow the exception. |
Worse area, same real slack | Target tighter than the requirement | Constrain the real target; move margin to variation. |
Silent stale exceptions | RTL changed under old constraints | Re-check exceptions after each RTL change. |
Unconstrained paths. The tool optimises them without a target, which risks closure.
Over-constraining. The tool spends area chasing a target tighter than the requirement.