This part closes the loop after optimisation and test hooks exist. Equivalence proves the netlist matches the RTL, and incremental compile and ECO handle late changes. Physical-aware estimates and a handoff package carry the result into layout.
Topic | Lessons | Description | Time |
|---|---|---|---|
5 | Proving the netlist equals the RTL, and reading a failure. | 40 min | |
5 | Re-run versus patch, spare cells, and keeping equivalence through an ECO. | 40 min | |
5 | Wire estimates, congestion, and the handoff package to physical design. | 40 min |
The patch may change function on untested vectors. The Equivalence Checking topic shows how a miter catches exactly that.