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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
    • Area, Power and Timing Trade-offs
    • Clock Gating and Low Power
    • DFT and Scan Insertion
      • The Scan Flop and Shift
      • DFT-Friendly RTL
      • Chain Stitching and Balancing
      • Scan Overhead in Area and Timing
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
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‹DFT and Scan Insertion
  1. Topics
  2. Logic Synthesis
  3. Area, Power and Test
  4. DFT and Scan Insertion
  5. Scan Overhead in Area and Timing

Part 6 · Area, Power and Test · Intermediate

Scan Overhead in Area and Timing

Scan cost in area units, timing slack, and test time with EXAMPLE numbers.

On this page

    Area overhead

    Each scan flop adds one 2-to-1 mux on its data input. In the course teaching library a DFF costs 8 area units and a MUX2 costs 5, so a scan flop costs 13 units.

    The calc block prices one thousand flops. The muxes add 5000 library units, a 62.5% overhead on the flop array before routing.

    Diagram
    course.lib teaching areas (library units, not a process): DFF = 8, MUX2 = 5
    scan flop = 8 + 5 = 13 units
    1000 plain flops = 1000 x 8 = 8000 units
    1000 scan flops = 1000 x 13 = 13000 units
    mux overhead = 13000 - 8000 = 5000 units = 5000 / 8000 = 62.5%

    Block

    Area (library units)

    Share of scan flop

    Flop (DFF)

    8

    8 / 13 = 61.54%

    Scan mux (MUX2)

    5

    5 / 13 = 38.46%

    Scan flop total

    13

    61.54 + 38.46 = 100.00%

    Timing overhead

    The scan mux adds delay to the functional data path. Arrival grows by the mux delay and slack, defined as required minus arrival, shrinks by the same amount.

    The calc block uses stated EXAMPLE parameters. SE itself switches only between phases, so it carries no cycle-to-cycle timing pressure.

    Diagram
    stated EXAMPLE parameters: scan mux delay 0.04 ns, required time 1.50 ns
    arrival before scan = 1.20 ns
    slack before = 1.50 - 1.20 = 0.30 ns
    arrival after scan mux = 1.20 + 0.04 = 1.24 ns
    slack after = 1.50 - 1.24 = 0.26 ns
    slack lost to the mux = 0.30 - 0.26 = 0.04 ns

    Test time and routing cost

    Test time is shift cycles times the shift-clock period, usually a slow EXAMPLE tester rate. Extra chains cut cycles but each chain needs pins and routing across the floorplan.

    The calc block extends the [4, 3, 3] example to five patterns. Forty-five cycles at 40 ns need 1.8 us of tester time.

    Diagram
    L = 4, per pattern = 4 + 1 + 4 = 9 cycles
    5 patterns = 5 x 9 = 45 cycles
    EXAMPLE shift period 40 ns (stated example parameter)
    test time = 45 x 40 ns = 1800 ns = 1.8 us

    Common pitfall

    Quoting test time from cycle counts alone misleads. Multiply by the tester period: slow shift clocks turn small cycle savings into large time savings.

    Interview

    Likely probes: pricing scan in three numbers.

    • Area: one MUX2 per flop, 62.5% on the flop array in course.lib units.

    • Timing: the mux delay leaves the data-path slack directly.

    • Test time: cycles times the EXAMPLE tester period, cut by balancing.

    Check yourself A path arrives at 1.20 ns against 1.50 ns required. What slack remains after a 0.04 ns scan mux?

    0.26 ns. Arrival rises to 1.24 ns, so 1.50 minus 1.24 leaves 0.26 ns.

    Check yourself Five patterns need 45 shift-inclusive cycles at an EXAMPLE 40 ns period. What is the test time?

    1800 ns, or 1.8 us. Cycle savings from balancing multiply by this period.

    Related topics

    • Chain Stitching and Balancing

    • Area, Power and Timing Trade-offs

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    See also

    • The Scan Flop and Shift
    • DFT-Friendly RTL