Clock gating cuts dynamic power by stopping toggles where work is idle. Latch-based cells gate the clock without glitches, operand isolation extends the idea into the datapath, and power intent records the rest as data.
Technique | What it stops | Where it lives |
|---|---|---|
Latch-based clock gating | Clock-pin toggles of idle flops | Integrated gating cell on the clock path. |
Operand isolation | Datapath toggles behind an idle block | Extra gating on block inputs. |
Multi-Vt mixing | Leakage on non-critical paths | Cell choice per timing slack. |
Power intent (UPF) | Nothing directly; it records domains | Side file describing retention and isolation. |
Lesson | What it covers |
|---|---|
The glitch hazard of AND gating and how the latch cell avoids it. | |
Enable-flop recognition in Yosys with asserted counts. | |
Power with and without gating from stated activity factors. | |
Freezing idle datapath inputs to stop wasted toggles. | |
Multi-Vt mixing, retention and isolation cells, UPF as intent only. |
Clock gating stops the clock edges at the flops. Operand isolation freezes the multiplier inputs.