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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
    • Area, Power and Timing Trade-offs
    • Clock Gating and Low Power
      • Latch-Based Gating versus AND Gating
      • Enable Flops and the Gating Opportunity
      • Switching-Activity Power Model
      • Operand Isolation
      • Power Intent, Multi-Vt and UPF
    • DFT and Scan Insertion
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
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‹Clock Gating and Low Power
  1. Topics
  2. Logic Synthesis
  3. Area, Power and Test
  4. Clock Gating and Low Power
  5. Operand Isolation

Part 6 · Area, Power and Test · Intermediate

Operand Isolation

Freezing idle datapath inputs to stop wasted toggles.

On this page

    Idle datapaths still toggle

    Clock gating stops the flops, but the combinational logic ahead of them keeps churning. A multiplier with live inputs burns toggles even when its result is discarded.

    Operand isolation freezes the block inputs while the block is idle. Downstream gates then see steady values and stop switching.

    Freezing the inputs

    The usual form holds each operand steady with the idle signal. A mux recirculates the old value, or simple gating forces a quiet constant.

    The select that marks the result unused doubles as the isolation condition. No new control logic is needed when that signal already exists.

    Diagram
    EXAMPLE activity (stated parameters):
    32-bit multiplier operand, mean 16 bits toggle per cycle while live
    block idle 3 cycles in 4, isolation freezes the operand while idle
    toggles per 4 cycles without isolation = 4 x 16 = 64
    toggles per 4 cycles with isolation = 1 x 16 = 16
    blocked toggles = 64 - 16 = 48 of 64 = 75%

    Costs and limits

    Isolation adds gates on the datapath inputs. Those gates sit on the timing path, so a critical operand may not afford them.

    Situation

    Cheaper answer

    Why

    Idle flops

    Clock gating

    Stops the clock pins directly with one cell.

    Idle datapath, loose timing

    Operand isolation

    Freezes wide inputs with a few extra gates.

    Idle for thousands of cycles

    Power gating as intent

    Clock and leakage both stop, at far higher control cost.

    Common mistakes

    Isolating to a constant that the downstream logic treats as live work defeats the purpose. Freeze to a value the idle block genuinely ignores.

    Common pitfall

    Isolating only one operand of a multiplier halves the saving at best. Freeze every toggling input of the idle block, or the uncovered one keeps the whole cone churning.

    Interview

    Likely probes: when isolation wins and what it costs.

    • It wins on wide datapaths that sit idle with live inputs.

    • Its gates load the operand timing path, so critical paths may be exempt.

    • The 48-of-64 blocked toggles follow from the stated 3-in-4 idle rate.

    Check yourself A block is idle 3 cycles in 4 and its operand toggles 16 bits per live cycle. How many toggles per 4 cycles does isolation block?

    48 of 64. Without isolation all 4 cycles toggle; with isolation only the 1 live cycle does.

    Check yourself The multiplier result is discarded but its inputs still toggle. Clock gating is already on. What further step helps?

    Operand isolation on the multiplier inputs. Clock gating stops the flops, while isolation stops the combinational churn ahead of them.

    Related topics

    • Switching-activity power model

    • Power intent, multi-Vt and UPF

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    See also

    • Latch-Based Gating versus AND Gating
    • Enable Flops and the Gating Opportunity