An idle register bank needs no clock edges. Gating stops the edges before they reach the flop clock pins.
The gated clock still drives real loads. Its buffers and skew behave like any other clock branch.
A bare AND gate combines the clock with the enable directly. Any enable move while the clock is high passes straight to the output.
A late enable edge inside the high phase makes a runt pulse. Some flops may catch it while others miss it.
EXAMPLE timing (stated parameters, not silicon data):
clock period 4 ns, high phase 2 ns
enable rises 0.5 ns after a rising edge
AND-gated clock follows at once, so a runt pulse of 2 - 0.5 = 1.5 ns reaches the flops
the latch-based cell holds enable steady through the high phase, so no pulse escapesThe integrated cell puts a level-sensitive latch ahead of the AND gate. The latch is transparent while the clock is low and holds while the clock is high.
Enable can only move the AND input during the low phase. The gated clock then rises and falls cleanly with the source clock.
Scheme | Enable path | Hazard |
|---|---|---|
Bare AND gate | Enable straight into the AND | Enable moves in the high phase escape as runt pulses. |
Latch-based cell | Enable through a latch open in the low phase | Enable is frozen during the high phase, so no runt pulse. |
An enable that comes from flops on the same clock is synchronous by construction. An asynchronous enable needs synchronising first, or the latch cannot promise clean gating.
1.5 ns. The output follows enable for the rest of the high phase: 2 minus 0.5.
Its latch holds enable steady while the clock is high. Enable can only reach the AND gate during the low phase.