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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
    • Area, Power and Timing Trade-offs
    • Clock Gating and Low Power
      • Latch-Based Gating versus AND Gating
      • Enable Flops and the Gating Opportunity
      • Switching-Activity Power Model
      • Operand Isolation
      • Power Intent, Multi-Vt and UPF
    • DFT and Scan Insertion
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
Loading lesson

‹Clock Gating and Low Power
  1. Topics
  2. Logic Synthesis
  3. Area, Power and Test
  4. Clock Gating and Low Power
  5. Switching-Activity Power Model

Part 6 · Area, Power and Test · Intermediate

Switching-Activity Power Model

Dynamic power with and without gating from stated activity factors.

On this page

    The dynamic power formula

    Switching power follows P = alpha x C x V^2 x f. Alpha is the mean toggles per cycle, C the switched capacitance, V the supply, and f the clock rate.

    Every number here is a stated EXAMPLE parameter. Real values vary with the library, the workload, and the operating point.

    Symbol

    Meaning

    EXAMPLE value

    C

    Switched capacitance of the gated domain

    100 pF

    V

    Supply voltage

    0.8 V

    f

    Clock rate

    500 MHz

    alpha ungated

    Clock toggles every cycle

    1.00

    alpha gated

    Enable active 1 cycle in 4, then 1 in 10

    0.25, then 0.10

    Worked comparison

    Substitute the EXAMPLE parameters for the ungated clock first. Then scale by the gated activity factors.

    Diagram
    EXAMPLE parameters (not silicon data): C = 100 pF, V = 0.8 V, f = 500 MHz
    ungated clock, alpha = 1.00:
    P = 1.00 x 100e-12 F x (0.8 V)^2 x 500e6 Hz
      = 100e-12 x 0.64 x 500e6 = 64e-12 x 500e6 = 32000e-6 W = 32.0 mW
    gated, enable active 1 cycle in 4, alpha = 0.25:
    P = 0.25 x 32.0 mW = 8.0 mW
    saving = 32.0 - 8.0 = 24.0 mW = 75.0%
    gated harder, enable active 1 cycle in 10, alpha = 0.10:
    P = 0.10 x 32.0 mW = 3.2 mW
    saving = 32.0 - 3.2 = 28.8 mW = 90.0%

    A runnable model

    The program below replays the hand arithmetic and checks all five results. It proves the code agrees with the worked comparison.

    example.py
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    import sys
    
    C = 100e-12
    V = 0.8
    F = 500e6
    
    def dyn_power(alpha):
        return alpha * C * V * V * F
    
    p_ungated = dyn_power(1.0)
    p_gate25 = dyn_power(0.25)
    p_gate10 = dyn_power(0.10)
    
    def close(got, want):
        return abs(got - want) < 1e-12
    
    checks = [
        (p_ungated, 0.032),
        (p_gate25, 0.008),
        (p_gate10, 0.0032),
        ((p_ungated - p_gate25) / p_ungated, 0.75),
        ((p_ungated - p_gate10) / p_ungated, 0.90),
    ]
    
    for i in range(len(checks)):
        got, want = checks[i]
        if not close(got, want):
            print("FAIL: check " + str(i + 1) + " got " + str(got) + " want " + str(want))
            sys.exit(1)
    
    print("PASS: gated model gives 8.0 mW at 25 percent enable and 3.2 mW at 10 percent")

    Common mistakes

    The arithmetic is exact for the stated alpha, but the formula is only the switching term: real power adds short-circuit, glitch and leakage terms, so alpha is not the only uncertainty. Measure or bound the enable rate before quoting the saving.

    Common pitfall

    Quoting 75% without the alpha behind it hides the assumption. Always attach the activity factor: 75% at alpha 0.25 against an ungated alpha of 1.00.

    Interview

    Likely probes: the formula and what moves the answer.

    • Power scales linearly with alpha and frequency, and with the square of the voltage.

    • The 24.0 mW saving is 75.0% only at the stated 1-in-4 enable rate.

    • The program checks five values: 0.032, 0.008, 0.0032, 0.75 and 0.90.

    Check yourself Voltage drops from 0.8 V to 0.7 V with alpha, C and f fixed. By what factor does power move?

    By (0.7 / 0.8)^2 = 0.7656, about 0.77x. Voltage enters squared while the rest enter linearly.

    Check yourself All five program checks pass. What does that prove, and what does it leave open?

    It proves the code agrees with the hand-worked totals. It leaves open the EXAMPLE activity factors, and the short-circuit, glitch and leakage terms the switching-only formula omits.

    Related topics

    • Enable flops and the gating opportunity

    • Operand isolation

    • Area, Power and Timing Trade-offs

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    See also

    • Latch-Based Gating versus AND Gating
    • Power Intent, Multi-Vt and UPF