The enable pattern

An enable flop keeps its value unless the enable is set. The RTL pattern is one line: on each clock, update only when the enable holds.

Synthesis builds a flop with a feedback mux on its data input. The mux recirculates the old value while the enable is low.

The gating opportunity in Yosys

The script below builds four enabled flops beside four free-running flops. Its two assertions pin the structure the lesson claims.

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read_verilog <<EOV
module gated(input wire clk, input wire en,
  input wire d0, input wire d1, input wire d2, input wire d3,
  input wire e0, input wire e1, input wire e2, input wire e3,
  output wire [3:0] q, output wire [3:0] f);
reg r0; reg r1; reg r2; reg r3;
reg s0; reg s1; reg s2; reg s3;
always @(posedge clk) if (en) r0 <= d0;
always @(posedge clk) if (en) r1 <= d1;
always @(posedge clk) if (en) r2 <= d2;
always @(posedge clk) if (en) r3 <= d3;
always @(posedge clk) s0 <= e0;
always @(posedge clk) s1 <= e1;
always @(posedge clk) s2 <= e2;
always @(posedge clk) s3 <= e3;
assign q = {r3, r2, r1, r0};
assign f = {s3, s2, s1, s0};
endmodule
EOV
hierarchy -check -top gated
proc
opt_clean
check
select -assert-count 8 t:$dff
select -assert-count 4 t:$mux
log PASS: 4 enable-mux flops mark the gating opportunity beside 4 free-running flops

What the tool does with it

The feedback mux is the marker the clock-gating step looks for. Each mux says the flop tolerates a stopped clock whenever the enable is low.

Which flops share one gating cell depends on the flow and the library. The opportunity is visible in any case; the grouping varies.

Common mistakes

An enable derived from deep combinational logic may arrive too late to gate with. The enable path has its own timing, and a late enable forces the clock back on.

Related topics

• Latch-based gating versus AND gating

• Switching-activity power model

• Flip-flops and registers