DFT and Scan Insertion · synthesis

Part 6 · Area, Power and Test · Intermediate

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Scan insertion makes every flop controllable and observable by stitching mux-D scan flops into shift chains. DFT-friendly RTL keeps that stitching cheap, and balanced chains keep test time short.

Term	Meaning
Scan flop	A flop with a data-select mux: functional data in normal mode, scan data in shift mode.
Scan enable (SE)	The mode select: low captures functional data, high shifts the chain.
Chain	Scan flops stitched output to input so one entry pin loads them all.
Capture	One functional clock with SE low that loads responses into the flops.
Balanced chains	Chains of near-equal length so no single long chain sets test time.

Two scan chains with scan entry pins and a shared capture pulse.

Two scan chains shift from shared entry pins and capture together.

Lesson	What it covers
The Scan Flop and Shift	Mux-D scan flops, scan enable, and shift and capture.
DFT-Friendly RTL	Testable clocks, resets, and the blockers that break scan.
Chain Stitching and Balancing	Partitioning flops into balanced chains with exact cycle counts.
Scan Overhead in Area and Timing	Mux area, slack cost, and test time with EXAMPLE numbers.

Check yourself Ten flops form one chain. How many shift cycles load a full pattern, and what sets that number?

Ten cycles, one per flop. Chain length sets test time directly, which is why balancing across chains matters.

Up nextThe Scan Flop and Shift

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