Every scan flop needs its shift clock in test mode. A gated clock that cannot be forced on leaves its flops unshiftable.
The standard fix is a test override that forces the gate open while SE is active. The gate still saves power in function and stays open through shift and capture.
Structure | Test problem | Fix |
|---|---|---|
Ungated flop clock | None: shifts and captures directly. | No change. |
Gated clock with test override | Gate could block shift if left functional. | Force the gate open in shift and capture. |
Gated clock without override | Flops behind it never shift. | Add the override or leave the clock ungated. |
Internally divided clock | Shift cannot reach its domain directly. | Bypass or control the divider in test mode. |
Capture assumes a known starting state, so every asynchronous reset needs a test-mode driver. An internally generated reset that cannot be asserted from a pin leaves unknown state.
Synchronous resets are ordinary data and shift like any logic. Asynchronous sets and resets get a test bypass back to their pins.
A combinational loop never settles, so capture results are undefined and shifting proves nothing. Break every loop in function, or open it with a test-mode mux.
Other blockers include tristate buses left floating and latches that the stitcher cannot order. Each one strands flops that scan cannot reach.
Blocker | Why scan fails | Fix |
|---|---|---|
Combinational loop | Logic never settles, so capture is undefined. | Break the loop or mux it open in test mode. |
Floating tristate bus | Unloaded value drifts, so capture varies. | Enable exactly one driver in test mode. |
Uncontrollable async reset | Starting state is unknown. | Drive the reset from a pin in test mode. |
Unordered latch | Shift order cannot be built through it. | Convert to a scan flop or bypass it. |
The calc block prices one missing override. Twelve stranded flops out of five hundred is a small share with a large consequence.
design total = 500 flops
flops behind a gated clock with no test override = 12
untestable share = 12 / 500 = 0.024 = 2.4%
testable flops = 500 - 12 = 488 = 97.6%
2.4 + 97.6 = 100.0Those twelve flops stop shifting, so patterns cannot cover their logic. The cheapest fix is a test-mode override that forces the gate open.
2.4%. A small share still forces a full re-stitch, so the override belongs in the RTL, not in a waiver.