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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
    • Equivalence Checking
    • Incremental Compile and ECO
    • Physical-Aware Synthesis and Handoff
      • Wire-Load Models and Placement Estimates
      • Congestion and Mapping Choices
      • Floorplan Assumptions
      • The Handoff Package
      • What Physical Design Changes
  • Flows and Debugging15
  • Interview and Judgment11
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‹Verification, ECO and Handoff
  1. Topics
  2. Logic Synthesis
  3. Verification, ECO and Handoff
  4. Physical-Aware Synthesis and Handoff

Part 7 · Verification, ECO and Handoff · Intermediate

Physical-Aware Synthesis and Handoff

Wire estimates, congestion, and the handoff package to physical design.

  • 5topics
  • 5lessons

Synthesis estimates wires before placement exists, and physical design changes what those estimates missed. The handoff package of netlist, constraints, library views, scan definition, and reports plus a sanity checklist keeps the boundary clean.

Term

Meaning

Wire-load model

A statistical fanout-to-length table used before any placement exists.

Placement-aware estimate

A length taken from a trial placement, per net rather than per fanout.

Congestion

Routing demand above routing supply in a region, guessed early from pin density.

Handoff package

Everything physical design needs: netlist, constraints, views, scan, reports.

From wire-load guess to handoff to physical changes.
Estimates improve toward handoff, and physical design still changes the result.

Lesson

What it covers

Wire-load models

Fanout tables against trial-placement lengths, with a worked delay estimate.

Congestion and mapping

A pin-density congestion proxy and why mapping choices matter physically.

Floorplan assumptions

Area, blockages, pin sides, and utilization arithmetic synthesis depends on.

Handoff package

Package contents, an illustrative constraint sketch, and the handoff checklist.

After-handoff changes

What physical design changes, correlation, and a netlist sanity checker.

Check yourself The synthesis report meets timing but placement fails it. What broke?

The wire estimate: synthesis timed ideal or modelled wires, and real routes added delay the estimate missed. Correlation, not the logic, is the suspect.

Interview

Carry one sentence per lesson: wire-load maps fanout to length while placement measures each net, pin density proxies congestion, the floorplan fixes area and pins, the handoff carries netlist plus constraints plus scan, and physical design re-buffers under equivalence.

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See also

  • Equivalence Checking
  • Incremental Compile and ECO