The floorplan fixes the ground synthesis stands on: core area, blocked regions, pin sides, and reserved grid. Every estimate downstream assumes these hold.
Fixed item | What synthesis assumes | If it changes |
|---|---|---|
Core area | Cells fit at the target utilization | Estimates go stale, hotspots move |
Blockages | No cells inside blocked rectilinear shapes | Logic piles beside the blockage |
Pin sides | Signals enter from stated edges | Nets cross the die to reach moved pins |
Grid reserve | Stated fraction kept for power routing | Supply tracks are missing where assumed |
Utilization is cell area over available area. Gross uses the whole core; net of blockages uses only free area.
Both numbers below are EXAMPLE parameters. Real targets vary by tool, library, and design style.
EXAMPLE areas: core 200 um x 500 um = 100000 um^2
cell area 60000 um^2 -> gross 60000 / 100000 = 0.60
blockage 20000 um^2 -> free 100000 - 20000 = 80000 um^2
net utilization = 60000 / 80000 = 0.75Late floorplan edits invalidate synthesis quietly. The netlist is unchanged, so no logical check fires, yet every physical estimate shifts.
Broken assumption | Symptom downstream | Response |
|---|---|---|
Pins moved to one side | Long detour nets, new critical paths | Re-budget IO timing, re-run placement-aware pass |
Blockage added late | Density spike beside the blockage | Re-spread logic, re-check the proxy |
Utilization raised | Router runs out of tracks | Recover area or accept a larger core |
Aspect ratio changed | Formerly short nets run long | Re-estimate before trusting old slack |
Synthesis keeps wire margin on critical nets because the floorplan may still move. Margin is cheaper than a loop back through the flow.
Over-margining has its own cost in area and power. The margin belongs on nets whose length is genuinely uncertain, not everywhere.
Gross is 0.60 and net is 0.75, since free area is 80000 square microns.
Nets that were short stubs now cross the die. Length and delay change while the gates stay the same.