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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
    • Equivalence Checking
    • Incremental Compile and ECO
    • Physical-Aware Synthesis and Handoff
      • Wire-Load Models and Placement Estimates
      • Congestion and Mapping Choices
      • Floorplan Assumptions
      • The Handoff Package
      • What Physical Design Changes
  • Flows and Debugging15
  • Interview and Judgment11
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‹Physical-Aware Synthesis and Handoff
  1. Topics
  2. Logic Synthesis
  3. Verification, ECO and Handoff
  4. Physical-Aware Synthesis and Handoff
  5. The Handoff Package

Part 7 · Verification, ECO and Handoff · Intermediate

The Handoff Package

Package contents, an illustrative constraint sketch, and the handoff checklist.

On this page

    What the package holds

    Physical design can only use what the handoff carries. A missing piece is rebuilt by guesswork, and guesswork reopens closed timing.

    Item

    Contents

    Consumer

    Gate-level netlist

    Mapped cells and wires, no behavioural constructs

    Placement and routing

    Timing constraints

    Clocks, IO delays, exceptions in SDC style

    Placement, clock tree, signoff

    Library views

    Timing, area, and physical views of every cell used

    Every downstream tool

    Scan definition

    Chains, order, clocking, and test modes

    Scan stitching and test

    Reports

    Area, timing, and quality snapshots with the run script

    Review and debug

    An illustrative constraint sketch

    The sketch below is illustrative only, not tool syntax. It shows the intent each constraint carries into physical design.

    Diagram
    illustrative sketch, not tool syntax:
    create_clock -period 2.0 on the clock port
    set_input_delay 0.4 relative to that clock on all inputs
    set_output_delay 0.4 relative to that clock on all outputs
    false paths on reset and test-mode selects

    The handoff checklist

    Every handoff answers each row before the netlist leaves. An unchecked row is a named owner and a date, never a shrug.

    Check

    Done means

    If missing

    Netlist matches constraints version

    Same revision on both, recorded

    IO timed against the wrong logic

    Every clock constrained

    Each clock created with period and source

    Untimed paths found at signoff

    Every IO delayed or excepted

    Input and output delay, or a false or multicycle path

    Route optimises the wrong paths

    Scan chains defined

    Order, clocks, and modes written down

    Stitching reorders or breaks timing

    Library views match cells

    No cell without timing and physical views

    Tool substitutes or stops

    Reports archived

    Area, timing, runs reproducible from the script

    Debug starts from rumour

    Common mistakes

    The classic failure is a stale constraint file beside a fresh netlist. Names drift, new ports arrive unconstrained, and the router polishes paths nobody cares about.

    Common pitfall

    Handing off the netlist without the exact constraints it closed against looks complete. Physical design then honours limits the logic never met and ignores ones it did.

    Interview

    Likely probes: listing the package from memory, and the stale-constraint failure.

    • Netlist, constraints, library views, scan definition, reports, run script.

    • Revision match between netlist and constraints is a checklist row of its own.

    • An unconstrained new port is optimised by luck, not by intent.

    Check yourself A new output port was added after constraints were written. What does the checklist demand?

    An input or output delay on it, or a documented exception. Unconstrained means untimed.

    Check yourself Scan chains were left out of the package. What breaks?

    Stitching order and test-mode timing get invented downstream. Scan definition belongs in the handoff.

    Related topics

    • After-handoff changes

    • DFT and scan insertion

    • Equivalence checking

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    See also

    • Wire-Load Models and Placement Estimates
    • Congestion and Mapping Choices