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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
    • SDC for Synthesis
      • Clocks and Generated Clocks
      • Uncertainty, Latency and IO Delays
      • Driving Cells, Loads and Units
      • False, Multicycle and Max-Delay Paths
      • Missing and Over-Tight Constraints
    • Delay Models and Slack
    • Timing-Driven Synthesis
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
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‹SDC for Synthesis
  1. Topics
  2. Logic Synthesis
  3. Constraints and Timing
  4. SDC for Synthesis
  5. Driving Cells, Loads and Units

Part 3 · Constraints and Timing · Intermediate

Driving Cells, Loads and Units

Drive and load bounds on ports, with EXAMPLE time and capacitance units.

On this page

    Driving cells

    A driving-cell bound names a library cell that the tool treats as driving an input port. It bounds the transition the input can present.

    The cell name refers to the teaching or project library in use. Stronger drive shortens the transition the tool assumes; weaker drive lengthens it.

    Loads

    A load bound states the capacitance the tool treats as hanging on an output port. It is an EXAMPLE parameter in femtofarads.

    Larger loads slow the output transition the tool computes. Each output needs its own bound when the loads differ.

    The listing below is illustrative tool-neutral SDC and is not run by any tool.

    Diagram
    illustrative SDC sketch (not run by any tool):
    set_driving_cell -lib_cell BUF [get_ports req]
    set_load 50.0 [get_ports ack]

    Units are EXAMPLE parameters

    Time is stated in nanoseconds and capacitance in femtofarads in this topic. Both are EXAMPLE units for hand arithmetic, not a claim about any tool or library.

    The unit convention in force varies with the library and tool setup. State the units alongside every number so the constraint is read as intended.

    Bound

    What it states

    EXAMPLE unit

    Driving cell

    Which cell model drives the input

    Cell name, such as BUF

    Load

    Capacitance on the output

    50.0 fF

    Delays and periods

    Time budgets from earlier lessons

    ns

    Common pitfall

    Leaving a port without a drive or load bound leaves the tool without an edge bound. What the tool assumes then varies, so an unstated assumption silently moves every IO result.

    Interview

    Likely probes: what each bound changes, and why units matter.

    • A driving cell bounds the input transition; a load sets the output capacitance.

    • Units are EXAMPLE parameters here: nanoseconds for time, femtofarads for capacitance.

    • Unit conventions vary with the library and tool setup, so state them explicitly.

    Check yourself An output carries set_load 50.0 with EXAMPLE units. What does the number mean?

    It means 50.0 fF of capacitance on that output in this topic's EXAMPLE units. Larger values slow the computed transition.

    Check yourself An input has no driving-cell bound. What is the risk?

    The tool works without an edge bound, and its assumption varies. State the drive explicitly instead.

    Related topics

    • False, Multicycle and Max-Delay Paths

    • Timing-Driven Synthesis

    • See also: RTL for Timing

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    See also

    • Clocks and Generated Clocks
    • Missing and Over-Tight Constraints